Apparatus and method for implementing power saving techniques when processing floating point values
Abstract
An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.
- Inventors:
- Issue Date:
- Research Org.:
- Intel Corporation, Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1397247
- Patent Number(s):
- 9779465
- Application Number:
- 14/581,600
- Assignee:
- Intel Corporation
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G06 - COMPUTING G06T - IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- DOE Contract Number:
- B600738
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014 Dec 23
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Kim, Young Moon, and Park, Sang Phill. Apparatus and method for implementing power saving techniques when processing floating point values. United States: N. p., 2017.
Web.
Kim, Young Moon, & Park, Sang Phill. Apparatus and method for implementing power saving techniques when processing floating point values. United States.
Kim, Young Moon, and Park, Sang Phill. Tue .
"Apparatus and method for implementing power saving techniques when processing floating point values". United States. https://www.osti.gov/servlets/purl/1397247.
@article{osti_1397247,
title = {Apparatus and method for implementing power saving techniques when processing floating point values},
author = {Kim, Young Moon and Park, Sang Phill},
abstractNote = {An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 03 00:00:00 EDT 2017},
month = {Tue Oct 03 00:00:00 EDT 2017}
}
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Works referenced in this record:
Method and apparatus for low power memory
patent, August 2003
- Burgess, Jr., Richard J.; Clark, Lawrence T.; Wagner, Kimberley E.
- US Patent Document 6,608,779
Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer
patent, October 2003
- Clift, David W.; Boggs, Darrell D.; Sager, David J.
- US Patent Document 6,633,970
Apparatus and method for reduction of processor power consumption
patent, April 2008
- Liron, Oded; Frank, Uri
- US Patent Document 7,363,464
Power saving in a floating point unit using a multiplier and aligner bypass
patent-application, September 2004
- Dhong, Sang; Mueller, Silvia; Oh, Hwa-Joon
- US Patent Application 10/392764; 20040186870
Zero Indication Forwarding for Floating Point Unit Power Reduction
patent-application, November 2012
- Barowski, Harry; Boersma, Maarten; Mueller, Silvia
- US Patent Application 13/552327; 20120284548
Approach to power reduction in floating-point operations
patent-application, May 2014
- Tannenbaum, David; Sprinkle, Colin; Oberman, Stuart
- US Patent Application 13/683362; 20140143564
Reducing the power consumption of memory devices
patent-application, June 2014
- Tercariol, Walter; Saez, Richard; da Silva, Jr., Afranio
- US Patent Application 13/709103; 20140160862
Adaptive Video Reference Frame Compression with Control Elements
patent-application, December 2014
- Wegener, Albert
- US Patent Application 13/907712; 20140355665
Apparatus and method for improving data storage by data inversion
patent-application, July 2015
- Kern, Thomas; Hofmann, Karl; Goessel, Michael
- US Patent Application 14/166360; 20150212877
Encoding for partitioned data bus
patent-application, August 2015
- Hollis, Timothy
- US Patent Application 14/175394; 20150229325