Store operations to maintain cache coherence
Abstract
In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1389845
- Patent Number(s):
- 9760487
- Application Number:
- 14/744,055
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B599858
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015 Jun 19
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Evangelinos, Constantinos, Nair, Ravi, and Ohmacht, Martin. Store operations to maintain cache coherence. United States: N. p., 2017.
Web.
Evangelinos, Constantinos, Nair, Ravi, & Ohmacht, Martin. Store operations to maintain cache coherence. United States.
Evangelinos, Constantinos, Nair, Ravi, and Ohmacht, Martin. Tue .
"Store operations to maintain cache coherence". United States. https://www.osti.gov/servlets/purl/1389845.
@article{osti_1389845,
title = {Store operations to maintain cache coherence},
author = {Evangelinos, Constantinos and Nair, Ravi and Ohmacht, Martin},
abstractNote = {In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {9}
}
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Works referenced in this record:
Multi-Petascale Highly Efficient Parallel Supercomputer
patent-application, September 2011
- Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.
- US Patent Document 13/004007; 20110219208
Sharing Virtual Functions in a Shared Virtual Memory between Heterogeneous Processors of a Computing Platform
patent-application, July 2013
- Yan, Shoumeng; Luo, Sai; Zhou, Xiaocheng
- US Patent Document 13/000621; 20130173894