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Title: Store operations to maintain cache coherence

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
Inventors:
; ;
Issue Date:
OSTI Identifier:
1373722
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
Patent Number(s):
9,720,832
Application Number:
14/671,050
Contract Number:
B599858
Resource Relation:
Patent File Date: 2015 Mar 27
Research Org:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Works referenced in this record:

Automatic software cache coherence through vectorization
conference, January 1992

The IBM RISC System/6000 processor: Hardware overview
journal, January 1990
  • Bakoglu, H. B.; Grohoski, G. F.; Montoye, R. K.
  • IBM Journal of Research and Development, Vol. 34, Issue 1, p. 12-22
  • DOI: 10.1147/rd.341.0012

Cohesion: a hybrid memory model for accelerators
conference, January 2010