Store operations to maintain cache coherence

Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

Title: Store operations to maintain cache coherence

Abstract

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

Inventors:: Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

Issue Date:: 2017-08-01

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1373722

Patent Number(s):: 9720832

Application Number:: 14/671,050

Assignee:: INTERNATIONAL BUSINESS MACHINES CORPORATION

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F2212/622 - State-only directory, i.e. not recording identity of sharing or owning nodes
G06F2212/1024 - Latency reduction
G06F2212/452 - Instruction code
G06F12/0875 - with dedicated cache, e.g. instruction or stack
G06F12/0837 - with software control, e.g. non-cacheable data
G06F12/0842 - for multiprocessing or multitasking
G06F8/4441 - {Reducing the execution time required by the program code}
G06F12/0815 - Cache consistency protocols

Show less

DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Mar 27

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Evangelinos, Constantinos, Nair, Ravi, and Ohmacht, Martin. Store operations to maintain cache coherence.  United States: N. p., 2017. 
        Web.

Copy to clipboard


                    Evangelinos, Constantinos, Nair, Ravi, & Ohmacht, Martin. Store operations to maintain cache coherence.  United States.

Copy to clipboard


                    Evangelinos, Constantinos, Nair, Ravi, and Ohmacht, Martin. Tue .  
        "Store operations to maintain cache coherence".  United States.  https://www.osti.gov/servlets/purl/1373722.

Copy to clipboard


                    
@article{osti_1373722,

  title        = {Store operations to maintain cache coherence},

  author       = {Evangelinos, Constantinos and Nair, Ravi and Ohmacht, Martin},

  abstractNote = {In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2017},

  month        = {8}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Automatic software cache coherence through vectorization
conference, January 1992

Darnell, Ervan; Mellor-Crummey, John M.; Kennedy, Ken
https://doi.org/10.1145/143369.143398

The IBM RISC System/6000 processor: Hardware overview
journal, January 1990

Bakoglu, H. B.; Grohoski, G. F.; Montoye, R. K.
IBM Journal of Research and Development, Vol. 34, Issue 1, p. 12-22
https://doi.org/10.1147/rd.341.0012

Cohesion: a hybrid memory model for accelerators
conference, January 2010

Kelm, John H.; Johnson, Daniel R.; Tuohy, William
https://doi.org/10.1145/1815961.1816019

Similar Records in DOE Patents and OSTI.GOV collections:

Store operations to maintain cache coherence

Patent Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
Full Text Available
Store-operate-coherence-on-value

Patent Chen, Dong; Heidelberger, Philip; Kumar, Sameer; ...

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the receivedmore » « less
Full Text Available
Light-weight cache coherence for data processors with limited data sharing

Patent Jayasena, Nuwan; Boyer, Michael

A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes amore » « less
Full Text Available
Cache as point of coherence in multiprocessor system

Patent Blumrich, Matthias A.; Ceze, Luis H.; Chen, Dong; ...

In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
Full Text Available
Locality-aware and sharing-aware cache coherence for collections of processors

Patent Farmahini Farahani, Amin; Jayasena, Nuwan

A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of themore » « less
Full Text Available

Similar Records

Title: Store operations to maintain cache coherence

Abstract

Citation Formats

Automatic software cache coherence through vectorization conference, January 1992

The IBM RISC System/6000 processor: Hardware overview journal, January 1990

Cohesion: a hybrid memory model for accelerators conference, January 2010

Automatic software cache coherence through vectorization
conference, January 1992

The IBM RISC System/6000 processor: Hardware overview
journal, January 1990

Cohesion: a hybrid memory model for accelerators
conference, January 2010