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Title: Method and apparatus for managing access to a memory

A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operational memory layout reduces an amount of energy consumed by the processor to perform the computing job.
Inventors:
Issue Date:
OSTI Identifier:
1373721
Assignee:
National Technologies & Engineering Solutions of Sandia, LLC SNL-A
Patent Number(s):
9,720,851
Application Number:
14/831,702
Contract Number:
AC04-94AL85000
Resource Relation:
Patent File Date: 2015 Aug 20
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Works referenced in this record:

175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor
conference, January 2006

Improvement of Electronic-Computer Reliability through the Use of Redundancy
journal, September 1961
  • Brown, W. G.; Tierney, J.; Wasserman, R.
  • IEEE Transactions on Electronic Computers, Vol. EC-10, Issue 3, p. 407-416
  • DOI: 10.1109/TEC.1961.5219229

Design of a Repairable Redundant Computer
journal, October 1962

Self-checked computation using residue arithmetic
journal, January 1966
  • Watson, R. W.; Hastings, C. W.
  • Proceedings of the IEEE, Vol. 54, Issue 12, p. 1920-1931
  • DOI: 10.1109/PROC.1966.5275

In Quest of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor
journal, December 2010

1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor
journal, April 2012
  • Karakiewicz, Rafal; Genov, Roman; Cauwenberghs, Gert
  • IEEE Sensors Journal, Vol. 12, Issue 4, p. 785-792
  • DOI: 10.1109/JSEN.2011.2113393

Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System
journal, July 2013
  • Chen, Jienan; Hu, Jianhao
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, Issue 7, p. 1322-1332
  • DOI: 10.1109/TVLSI.2012.2205953

A low-power sense amplifier for adiabatic memory using memristor
conference, December 2012

Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects
conference, January 2009

Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
conference, January 1999

A three-port adiabatic register file suitable for embedded applications
conference, January 1998