Method to pattern <10 micrometer conducting and passivating features on 3D substrates for implantable devices

Title: Method to pattern <10 micrometer conducting and passivating features on 3D substrates for implantable devices

An implantable device has a cylindrical base, at least one electrode on the cylindrical base, at least one electrically conducting lead on the cylindrical base connected to the electrode wherein the electrically conducting lead has a feature size of <10 micrometers. A protective coating on the cylindrical base covers the at least one electrically conducting lead.

Inventors:: Tolosa, Vanessa; Pannu, Satinderpall S.; Sheth, Heeral; Tooker, Angela C.; Shah, Kedar G.

Issue Date:: 2017-07-04

OSTI Identifier:: 1368352

Assignee:: Lawrence Livermore National Security, LLC LLNL

Patent Number(s):: 9,694,190

Application Number:: 14/213,733

Contract Number:: AC52-07NA27344

Resource Relation:: Patent File Date: 2014 Mar 14

Research Org:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org:: USDOE

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

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