Title: Low latency asynchronous interface circuits

Abstract

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

Inventors:

Sadowski, Greg

Issue Date:

Tue Jun 20 00:00:00 EDT 2017

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1364405

Patent Number(s):

9685953

Application Number:

15/261,438

Assignee:

ADVANCED MICRO DEVICES, INC.

Patent Classifications (CPCs):

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

H03K19/00315 - {in field-effect transistor circuits}
H03K19/018521 - {of complementary type, e.g. CMOS}
H03K19/01855 - {synchronous, i.e. using clock signals}

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DOE Contract Number:  

AC52-07NA27344

Resource Type:

Patent

Resource Relation:

Patent File Date: 2016 Sep 09

Country of Publication:

United States

Language:

English

Subject:

42 ENGINEERING