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Title: Method of making a silicon nanowire device

There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 .mu.m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation. The method, in examples, includes thinning the nanowire through iterative oxidation and etching of the oxidized portion.
Inventors:
Issue Date:
OSTI Identifier:
1358226
Assignee:
Sandia Corporation SNL-A
Patent Number(s):
9,660,026
Application Number:
15/354,196
Contract Number:
AC04-94AL85000
Resource Relation:
Patent File Date: 2016 Nov 17
Research Org:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Other works cited in this record:

Multiple orientation nanowires with gate stack stressors
patent, February 2013

Insulated gate silicon nanowire transistor and method of manufacture
patent-application, November 2007

Nanowire Fet Having Induced Radial Strain
patent-application, June 2011

Generation Of Multiple Diameter Nanowire Field Effect Transistors
patent-application, November 2011

Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric
patent-application, January 2012

Nanowires, Nanowire Fielde-Effect Transistors And Fabrication Method
patent-application, June 2014

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