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Title: Silent store detection and recording in memory storage

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.
Inventors:
; ;
Issue Date:
OSTI Identifier:
1346041
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
Patent Number(s):
9,588,767
Application Number:
14/749,680
Contract Number:
B599858
Resource Relation:
Patent File Date: 2015 Jun 25
Research Org:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Works referenced in this record:

Characterization of silent stores
conference, January 2000
  • Bell, G.B.; Lepak, K.M.; Lipasti, M.H.
  • International Conference on Parallel Architectures and Compilation Techniques
  • DOI: 10.1109/PACT.2000.888338

Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache
book, January 2006
  • Kucuk, Gurhan; Basaran, Can; Hutchison, David
  • Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p. 256-266
  • DOI: 10.1007/11847083_25

Performance and environment monitoring for continuous program optimization
journal, March 2006
  • Cascaval, C.; Duesterwald, E.; Sweeney, P. F.
  • IBM Journal of Research and Development, Vol. 50, Issue 2.3, p. 239-248
  • DOI: 10.1147/rd.502.0239

Eliminating squashes through learning cross-thread violations in speculative parallelization for multiprocessors
conference, January 2002
  • Cintra, M.; Torrellas, J.
  • Eighth International Symposium on High-Performance Computer Architecture
  • DOI: 10.1109/HPCA.2002.995697

Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE
conference, January 2005
  • Corliss, M.L.; Lewis, E.C.; Roth, A.
  • 11th International Symposium on High-Performance Computer Architecture
  • DOI: 10.1109/HPCA.2005.18