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Title: Semiconductor structure and recess formation etch technique

A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.
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Issue Date:
OSTI Identifier:
Massachusetts Institute of Technology ARPA-E
Patent Number(s):
Application Number:
Contract Number:
Resource Relation:
Patent File Date: 2013 Nov 15
Research Org:
Massachusetts Institute of Technology, Cambridge, MA (United States)
Sponsoring Org:
Country of Publication:
United States

Other works cited in this record:

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Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
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Two stage plasma etching method for enhancement mode GaN HFET
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Compound semiconductor device and method of manufacturing the same
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journal, November 2008
  • Chu, Rongming; Chen, Zhen; DenBaars, Steven P.
  • IEEE Electron Device Letters, Vol. 29, Issue 11, p. 1184-1186
  • DOI: 10.1109/LED.2008.2004721

AlGaN/GaN HEMT With 300-GHz fmax
journal, March 2010
  • Chung, J. W.; Hoke, W. E.; Chumbes, E. M.
  • IEEE Electron Device Letters, Vol. 31, Issue 3, p. 195-197
  • DOI: 10.1109/LED.2009.2038935

Enhancement-Mode GaN MIS-HEMTs With n-GaN/i-AlN/n-GaN Triple Cap Layer and High- k Gate Dielectrics
journal, March 2010
  • Kanamura, M.; Ohki, T.; Kikkawa, T.
  • IEEE Electron Device Letters, Vol. 31, Issue 3, p. 189-191
  • DOI: 10.1109/LED.2009.2039026

Digital etching of III-N materials using a two-step Ar/KOH technique
journal, April 2006
  • Keogh, David; Asbeck, Peter; Chung, Theodore
  • Journal of Electronic Materials, Vol. 35, Issue 4, p. 771-776
  • DOI: 10.1007/s11664-006-0137-6

An Etch-Stop Barrier Structure for GaN High-Electron-Mobility Transistors
journal, March 2013
  • Lu, Bin; Sun, Min; Palacios, T.
  • IEEE Electron Device Letters, Vol. 34, Issue 3, p. 369-371
  • DOI: 10.1109/LED.2012.2237374

High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor
journal, September 2010
  • Lu, Bin; Saadat, Omair Irfan; Palacios, Tom├ís
  • IEEE Electron Device Letters, Vol. 31, Issue 9, p. 990-992
  • DOI: 10.1109/LED.2010.2055825

Nitride-based high electron mobility transistors with a GaN spacer
journal, August 2006
  • Palacios, T.; Shen, L.; Keller, S.
  • Applied Physics Letters, Vol. 89, Issue 7, Article No. 073508
  • DOI: 10.1063/1.2335514

Origin and passivation of fixed charge in atomic layer deposited aluminum oxide gate insulators on chemically treated InGaAs substrates
journal, April 2010
  • Shin, Byungha; Weber, Justin R.; Long, Rathnait D.
  • Applied Physics Letters, Vol. 96, Issue 15, Article No. 152908
  • DOI: 10.1063/1.3399776

Fabrication of Normally Off AlGaN/GaN MOSFET Using a Self-Terminating Gate Recess Etching Technique
journal, July 2013
  • Xu, Zhe; Wang, Jinyan; Liu, Yang
  • IEEE Electron Device Letters, Vol. 34, Issue 7, p. 855-857
  • DOI: 10.1109/LED.2013.2264494

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