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Title: Schedulers with load-store queue awareness

In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.
Inventors:
; ; ;
Issue Date:
OSTI Identifier:
1343283
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION OSTI
Patent Number(s):
9,563,428
Application Number:
14/669,472
Contract Number:
B599858
Resource Relation:
Patent File Date: 2015 Mar 26
Research Org:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Other works cited in this record:

Circuit and method for scheduling instructions by predicting future availability of resources required for execution
patent, September 1996

Scheduling instructions with different latencies
patent, March 2000

Method for alternate preferred time delivery of load data
patent, May 2002

System and method for scheduling instructions to maximize outstanding prefetches and loads
patent, July 2005

Dynamic resizing of superscalar datapath components for energy efficiency
journal, February 2006
  • Ponomarev, D.; Kucuk, G.; Ghose, K.
  • IEEE Transactions on Computers, Vol. 55, Issue 2, p. 199-213
  • DOI: 10.1109/TC.2006.23

An analysis of finite capacity queues with priority scheduling and common or reserved waiting areas
journal, January 1989

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