Schedulers with load-store queue awareness
Abstract
In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1340538
- Patent Number(s):
- 9552196
- Application Number:
- 14/744,051
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B599858
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2015 Jun 19
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Chen, Tong, Eichenberger, Alexandre E., Jacob, Arpith C., and Sura, Zehra N. Schedulers with load-store queue awareness. United States: N. p., 2017.
Web.
Chen, Tong, Eichenberger, Alexandre E., Jacob, Arpith C., & Sura, Zehra N. Schedulers with load-store queue awareness. United States.
Chen, Tong, Eichenberger, Alexandre E., Jacob, Arpith C., and Sura, Zehra N. Tue .
"Schedulers with load-store queue awareness". United States. https://www.osti.gov/servlets/purl/1340538.
@article{osti_1340538,
title = {Schedulers with load-store queue awareness},
author = {Chen, Tong and Eichenberger, Alexandre E. and Jacob, Arpith C. and Sura, Zehra N.},
abstractNote = {In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2017},
month = {1}
}
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Scheduling instructions with different latencies
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System and method for scheduling instructions to maximize outstanding prefetches and loads
patent, July 2005
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