Processor register error correction management

Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

Title: Processor register error correction management

Abstract

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Inventors:: Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

Issue Date:: 2016-12-27

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1337630

Patent Number(s):: 9529653

Application Number:: 14/510,350

Assignee:: International Business Machines Corporation (Armonk, NY

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1666 - {where the redundant component is memory or memory area}
G06F11/0793 - {Remedial or corrective actions
G06F11/073 - {in a memory management context, e.g. virtual memory or cache management
G06F11/20 - using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F11/0721 - {within a central processing unit [CPU]}

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DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014 Oct 09

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Bose, Pradip, Cher, Chen-Yong, and Gupta, Meeta S. Processor register error correction management.  United States: N. p., 2016. 
        Web.

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                    Bose, Pradip, Cher, Chen-Yong, & Gupta, Meeta S. Processor register error correction management.  United States.

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                    Bose, Pradip, Cher, Chen-Yong, and Gupta, Meeta S. Tue .  
        "Processor register error correction management".  United States.  https://www.osti.gov/servlets/purl/1337630.

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@article{osti_1337630,

  title        = {Processor register error correction management},

  author       = {Bose, Pradip and Cher, Chen-Yong and Gupta, Meeta S.},

  abstractNote = {Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {12}

}

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Works referenced in this record:

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conference, October 2014

Cher, Chen-Yong; Muller, K. Paul; Haring, Ruud A.
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Flikker: saving DRAM refresh-power through critical data partitioning
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Liu, Song; Pattabiraman, Karthik; Moscibroda, Thomas
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journal, June 2011

Loveless, T. D.; Jagannathan, S.; Reece, T.
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Assessment of the Impact of Cosmic-Ray-Induced Neutrons on Hardware in the Roadrunner Supercomputer
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Technologies to further reduce soft error susceptibility in SOI
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Oldiges, P.; Dennard, R.; Heidel, D.
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SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
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IEEE Transactions on Nuclear Science, Vol. 58, Issue 6
https://doi.org/10.1109/TNS.2011.2171715

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Similar Records

Title: Processor register error correction management

Abstract

Citation Formats

Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation conference, October 2014

Exploring event correlation for failure prediction in coalitions of clusters conference, January 2007

SECRET: Selective error correction for refresh energy reduction in DRAMs conference, September 2012

Flikker: saving DRAM refresh-power through critical data partitioning journal, March 2011

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node journal, June 2011

Assessment of the Impact of Cosmic-Ray-Induced Neutrons on Hardware in the Roadrunner Supercomputer journal, June 2012

Technologies to further reduce soft error susceptibility in SOI conference, December 2009

SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs conference, January 2005

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches journal, December 2011

Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation
conference, October 2014

Exploring event correlation for failure prediction in coalitions of clusters
conference, January 2007

SECRET: Selective error correction for refresh energy reduction in DRAMs
conference, September 2012

Flikker: saving DRAM refresh-power through critical data partitioning
journal, March 2011

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node
journal, June 2011

Assessment of the Impact of Cosmic-Ray-Induced Neutrons on Hardware in the Roadrunner Supercomputer
journal, June 2012

Technologies to further reduce soft error susceptibility in SOI
conference, December 2009

SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
conference, January 2005

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches
journal, December 2011