Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute

Chiu, George L.; Eichenberger, Alexandre E.; O'Brien, John K. P.

Title: Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute

Abstract

The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.

Inventors:: Chiu, George L.; Eichenberger, Alexandre E.; O'Brien, John K. P.

Issue Date:: 2016-12-13

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1335817

Patent Number(s):: 9519583

Application Number:: 14/963,918

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0811 - with multilevel cache hierarchies
G06F2209/5018 - Thread allocation
G06F2212/283 - Plural cache memories
G06F9/3838 - {Dependency mechanisms, e.g. register scoreboarding}
G06F9/3851 - {from multiple instruction streams, e.g. multistreaming
G06F9/3861 - {Recovery, e.g. branch miss-prediction, exception handling
G06F9/5016 - {the resource being the memory}
G06F9/5027 - {the resource being a machine, e.g. CPUs, Servers, Terminals}
G06F9/52 - Program synchronisation
G06F9/544 - {Buffers

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C7/1072 - {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Dec 09

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Chiu, George L., Eichenberger, Alexandre E., and O'Brien, John K. P.. Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.  United States: N. p., 2016. 
        Web.

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                    Chiu, George L., Eichenberger, Alexandre E., & O'Brien, John K. P.. Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.  United States.

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                    Chiu, George L., Eichenberger, Alexandre E., and O'Brien, John K. P.. Tue .  
        "Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute".  United States.  https://www.osti.gov/servlets/purl/1335817.

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@article{osti_1335817,

  title        = {Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute},

  author       = {Chiu, George L. and Eichenberger, Alexandre E. and O'Brien, John K. P.},

  abstractNote = {The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {12}

}

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Works referenced in this record:

Concurrency control of state machines in a computer system using cliques
patent, December 2000

Chopra, Gagan; McCline, Matthew C.; Helland, Patrick James
US Patent Document 6,167,423
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6167423

Apparatus, method and system for aggregrating computing resources
patent, May 2008

Miloushev, Vladimir; Nickolov, Peter; Hester, Becky L.
US Patent Document 7,380,039
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7380039

Method and system for maintaining consistency during multi-threaded processing of LDIF data
patent, June 2009

Alexander, III, William Preston; Kuiper, Kean G.; Richardson, Christopher Michael
US Patent Document 7,548,989
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7548989

Thread monitoring using shared memory
patent, March 2010

Dostert, Jan; Fleischer, Christian; Kilian, Frank
US Patent Document 7,689,989
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7689989

Method and apparatus for detecting cross-thread stack access in multithreaded programs
patent, November 2010

Ma, Zhiqiang; Petersen, Paul M.
US Patent Document 7,844,971
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7844971

Method, system, and computer readable medium useful in managing a computer-based system for servicing user initiated tasks
patent, January 2011

Jones, Scott A.; Cooper, Thomas E.
US Patent Document 7,873,532
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7873532

Data structure and management techniques for local user-level thread data
patent, December 2011

Hankins, Richard; Chinya, Gautham; Wang, Hong
US Patent Document 8,079,035
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8079035

Constant time worker thread allocation via configuration caching
patent, November 2014

Eichenberger, Alexandre E.; O'Brien, John Kevin Patrick
US Patent Document 8,881,159
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8881159

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Title: Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute

Abstract

Citation Formats

Concurrency control of state machines in a computer system using cliques patent, December 2000

Apparatus, method and system for aggregrating computing resources patent, May 2008

Method and system for maintaining consistency during multi-threaded processing of LDIF data patent, June 2009

Thread monitoring using shared memory patent, March 2010

Method and apparatus for detecting cross-thread stack access in multithreaded programs patent, November 2010

Method, system, and computer readable medium useful in managing a computer-based system for servicing user initiated tasks patent, January 2011

Data structure and management techniques for local user-level thread data patent, December 2011

Constant time worker thread allocation via configuration caching patent, November 2014

Concurrency control of state machines in a computer system using cliques
patent, December 2000

Apparatus, method and system for aggregrating computing resources
patent, May 2008

Method and system for maintaining consistency during multi-threaded processing of LDIF data
patent, June 2009

Thread monitoring using shared memory
patent, March 2010

Method and apparatus for detecting cross-thread stack access in multithreaded programs
patent, November 2010

Method, system, and computer readable medium useful in managing a computer-based system for servicing user initiated tasks
patent, January 2011

Data structure and management techniques for local user-level thread data
patent, December 2011

Constant time worker thread allocation via configuration caching
patent, November 2014