Memory hierarchy using row-based compression

Title: Memory hierarchy using row-based compression

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Abstract

A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

Inventors:: Loh, Gabriel H.; O'Connor, James M.

Issue Date:: 2016-10-25

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1330324

Patent Number(s):: 9,477,605

Application Number:: 13/939,377

Assignee:: Advanced Micro Devices, Inc. (Sunnyvale, CA)

DOE Contract Number:: AC52-07NA27344

Resource Type:: Patent

Resource Relation:: Patent File Date: 2013 Jul 11

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Loh, Gabriel H., and O'Connor, James M. Memory hierarchy using row-based compression.  United States: N. p., 2016. 
        Web.

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                    Loh, Gabriel H., & O'Connor, James M. Memory hierarchy using row-based compression.  United States.

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                    Loh, Gabriel H., and O'Connor, James M. Tue .  
        "Memory hierarchy using row-based compression".  United States.  https://www.osti.gov/servlets/purl/1330324.

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@article{osti_1330324,

  title        = {Memory hierarchy using row-based compression},

  author       = {Loh, Gabriel H. and O'Connor, James M.},

  abstractNote = {A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {10}

}

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