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Title: Method and apparatus for faulty memory utilization

A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.
Inventors:
; ; ; ;
Issue Date:
OSTI Identifier:
1247994
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
Patent Number(s):
9,317,350
Application Number:
14/022,171
Contract Number:
B599858
Resource Relation:
Patent File Date: 2013 Sep 09
Research Org:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Works referenced in this record:

Proactive process-level live migration and back migration in HPC environments
journal, February 2012
  • Wang, Chao; Mueller, Frank; Engelmann, Christian
  • Journal of Parallel and Distributed Computing, Vol. 72, Issue 2, p. 254-267
  • DOI: 10.1016/j.jpdc.2011.10.009