Single event upset protection circuit and method
Abstract
An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates `odd` parity, and to pass the redundant data value to the output when the parity engine output indicates `even` parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-CA), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1243318
- Patent Number(s):
- 9292378
- Application Number:
- 14/290,648
- Assignee:
- TELEDYNE SCIENTIFIC & IMAGING, LLC (Thousand Oaks, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014 May 29
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Wallner, John, and Gorder, Michael. Single event upset protection circuit and method. United States: N. p., 2016.
Web.
Wallner, John, & Gorder, Michael. Single event upset protection circuit and method. United States.
Wallner, John, and Gorder, Michael. Tue .
"Single event upset protection circuit and method". United States. https://www.osti.gov/servlets/purl/1243318.
@article{osti_1243318,
title = {Single event upset protection circuit and method},
author = {Wallner, John and Gorder, Michael},
abstractNote = {An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates `odd` parity, and to pass the redundant data value to the output when the parity engine output indicates `even` parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 22 00:00:00 EDT 2016},
month = {Tue Mar 22 00:00:00 EDT 2016}
}
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