Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Asaad, Sameh W.; Kapur, Mohit

Title: Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Abstract

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Inventors:: Asaad, Sameh W.; Kapur, Mohit

Issue Date:: 2016-03-15

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1243039

Patent Number(s):: 9286423

Application Number:: 13/435,707

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES
G01R31/2851 - {Testing of integrated circuits [IC]
G01R31/31703 - {Comparison aspects, e.g. signature analysis, comparators
G01R31/31727 - {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
G01R31/3177 - Testing of logic operation, e.g. by logic analysers

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F30/331 - with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2012 Mar 30

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Asaad, Sameh W., and Kapur, Mohit. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator.  United States: N. p., 2016. 
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                    Asaad, Sameh W., & Kapur, Mohit. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator.  United States.

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                    Asaad, Sameh W., and Kapur, Mohit. Tue .  
        "Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator".  United States.  https://www.osti.gov/servlets/purl/1243039.

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@article{osti_1243039,

  title        = {Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator},

  author       = {Asaad, Sameh W. and Kapur, Mohit},

  abstractNote = {A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {3}

}

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Works referenced in this record:

SoC HW/SW verification and validation
conference, January 2011

Chung-Yang Huang,
2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)
https://doi.org/10.1109/ASPDAC.2011.5722202

A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM
journal, January 2006

Cofler, A. M.; Druilhe, F.; Dutoit, D.
IEEE Journal of Solid-State Circuits, Vol. 41, Issue 1
https://doi.org/10.1109/JSSC.2005.859317

Intel® atom™ processor core made FPGA-synthesizable
conference, January 2009

Wang, Perry H.; Steibl, Sebastian; Wang, Hong
Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09
https://doi.org/10.1145/1508128.1508160

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
conference, January 2012

Asaad, Sameh; Tierno, José; Bellofatto, Ralph
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12
https://doi.org/10.1145/2145694.2145720

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Title: Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Abstract

Citation Formats

SoC HW/SW verification and validation conference, January 2011

A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM journal, January 2006

Intel® atom™ processor core made FPGA-synthesizable conference, January 2009

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation conference, January 2012

SoC HW/SW verification and validation
conference, January 2011

A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM
journal, January 2006

Intel® atom™ processor core made FPGA-synthesizable
conference, January 2009

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
conference, January 2012