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Title: Implementing inverted master-slave 3D semiconductor stack

Abstract

A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.

Inventors:
; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1241310
Patent Number(s):
9,281,302
Application Number:
14/184,868
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B601996
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 Feb 20
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; 42 ENGINEERING

Citation Formats

Coteus, Paul W., Hall, Shawn A., and Takken, Todd E. Implementing inverted master-slave 3D semiconductor stack. United States: N. p., 2016. Web.
Coteus, Paul W., Hall, Shawn A., & Takken, Todd E. Implementing inverted master-slave 3D semiconductor stack. United States.
Coteus, Paul W., Hall, Shawn A., and Takken, Todd E. Tue . "Implementing inverted master-slave 3D semiconductor stack". United States. https://www.osti.gov/servlets/purl/1241310.
@article{osti_1241310,
title = {Implementing inverted master-slave 3D semiconductor stack},
author = {Coteus, Paul W. and Hall, Shawn A. and Takken, Todd E.},
abstractNote = {A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {3}
}

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