DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator

Abstract

A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality of communicators for storing state information for a barrier algorithm. Each communicator designates a master core in a multi-processor environment of the computer system. The system allocates or designates one counter for each of a plurality of threads. The system configures a table with a number of entries equal to the maximum number of threads. The system sets a table entry with an ID associated with a communicator when a process thread initiates a collective. The system determines an allocated or designated counter by searching entries in the table.

Inventors:
; ; ; ;
Issue Date:
Research Org.:
GLOBALFOUNDRIES INC., Grand Cayman, KY (Cayman Islands)
Sponsoring Org.:
USDOE
OSTI Identifier:
1236466
Patent Number(s):
9244734
Application Number:
14/015,098
Assignee:
GLOBALFOUNDRIES INC.
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 Aug 30
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Blocksome, Michael, Kumar, Sameer, Mamidala, Amith R., Miller, Douglas, and Ratterman, Joseph D.. Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator. United States: N. p., 2016. Web.
Blocksome, Michael, Kumar, Sameer, Mamidala, Amith R., Miller, Douglas, & Ratterman, Joseph D.. Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator. United States.
Blocksome, Michael, Kumar, Sameer, Mamidala, Amith R., Miller, Douglas, and Ratterman, Joseph D.. Tue . "Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator". United States. https://www.osti.gov/servlets/purl/1236466.
@article{osti_1236466,
title = {Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator},
author = {Blocksome, Michael and Kumar, Sameer and Mamidala, Amith R. and Miller, Douglas and Ratterman, Joseph D.},
abstractNote = {A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality of communicators for storing state information for a barrier algorithm. Each communicator designates a master core in a multi-processor environment of the computer system. The system allocates or designates one counter for each of a plurality of threads. The system configures a table with a number of entries equal to the maximum number of threads. The system sets a table entry with an ID associated with a communicator when a process thread initiates a collective. The system determines an allocated or designated counter by searching entries in the table.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {1}
}

Works referenced in this record:

SMARTMAP: Operating system support for efficient data sharing among processes on a multi-core processor
conference, November 2008


Program thread syncronization for instruction cachelines
patent, June 2009


Measuring processor use in a hardware multithreading processor environment
patent, June 2009


Program thread syncronization
patent, July 2011


Thread-type-based load balancing in a multithreaded processor
patent, December 2011


Thread-type-based resource allocation in a multithreaded processor
patent, January 2012


Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state
patent, February 2012