Error recovery to enable error-free message transfer between nodes of a computer network

Blumrich, Matthias A.; Coteus, Paul W.; Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd; Steinmacher-Burow, Burkhard; Vranas, Pavlos M.

Title: Error recovery to enable error-free message transfer between nodes of a computer network

Full Record
Other Related Research

Abstract

An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.

Inventors:: Blumrich, Matthias A.; Coteus, Paul W.; Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd; Steinmacher-Burow, Burkhard; Vranas, Pavlos M.

Issue Date:: 2016-01-26

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1236465

Patent Number(s):: 9244759

Application Number:: 14/148,348

Assignee:: International Business Machines Corporation

Patent Classifications (CPCs):: H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L2001/0093 - {Point-to-multipoint}
H04L2001/0097 - {Relays}
H04L1/1867 - {Arrangements specific to the transmitter end}
H04L1/0061 - {Error detection codes}

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/46 - Multiprogramming arrangements
G06F11/1423 - {by reconfiguration of paths}

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L1/08 - by repeating transmission, e.g. Verdan system {
H04L1/1607 - {Details of the supervisory signal}

Show less

DOE Contract Number:: B517552

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014 Jan 06

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING; 99 GENERAL AND MISCELLANEOUS

Citation Formats


                    Blumrich, Matthias A., Coteus, Paul W., Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd, Steinmacher-Burow, Burkhard, and Vranas, Pavlos M. Error recovery to enable error-free message transfer between nodes of a computer network.  United States: N. p., 2016. 
        Web.

Copy to clipboard


                    Blumrich, Matthias A., Coteus, Paul W., Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd, Steinmacher-Burow, Burkhard, & Vranas, Pavlos M. Error recovery to enable error-free message transfer between nodes of a computer network.  United States.

Copy to clipboard


                    Blumrich, Matthias A., Coteus, Paul W., Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd, Steinmacher-Burow, Burkhard, and Vranas, Pavlos M. Tue .  
        "Error recovery to enable error-free message transfer between nodes of a computer network".  United States.  https://www.osti.gov/servlets/purl/1236465.

Copy to clipboard


                    
@article{osti_1236465,

  title        = {Error recovery to enable error-free message transfer between nodes of a computer network},

  author       = {Blumrich, Matthias A. and Coteus, Paul W. and Chen, Dong and Gara, Alan and Giampapa, Mark E. and Heidelberger, Philip and Hoenicke, Dirk and Takken, Todd and Steinmacher-Burow, Burkhard and Vranas, Pavlos M.},

  abstractNote = {An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {1}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Similar Records in DOE Patents and OSTI.GOV collections:

Signaling completion of a message transfer from an origin compute node to a target compute node

Patent Blocksome, Michael A [Rochester, MN]; Parker, Jeffrey J [Rochester, MN]

Signaling completion of a message transfer from an origin node to a target node includes: sending, by an origin DMA engine, an RTS message, the RTS message specifying an application message for transfer to the target node from the origin node; receiving, by the origin DMA engine, a remote get message containing a data descriptor for the message and a completion notification descriptor, the completion notification descriptor specifying a local direct put transfer operation for transferring data locally on the origin node; inserting, by the origin DMA engine in an injection FIFO buffer, the data descriptor followed by the completionmore » « less
Full Text Available
Signaling completion of a message transfer from an origin compute node to a target compute node

Patent Blocksome, Michael A [Rochester, MN]

Signaling completion of a message transfer from an origin node to a target node includes: sending, by an origin DMA engine, an RTS message, the RTS message specifying an application message for transfer to the target node from the origin node; receiving, by the origin DMA engine, a remote get message containing a data descriptor for the message and a completion notification descriptor, the completion notification descriptor specifying a local memory FIFO data transfer operation for transferring data locally on the origin node; inserting, by the origin DMA engine in an injection FIFO buffer, the data descriptor followed by themore » « less
Full Text Available
Message communications of particular message types between compute nodes using DMA shadow buffers

Patent Blocksome, Michael A [Rochester, MN]; Parker, Jeffrey J [Rochester, MN]

Message communications of particular message types between compute nodes using DMA shadow buffers includes: receiving a buffer identifier specifying an application buffer having a message of a particular type for transmission to a target compute node through a network; selecting one of a plurality of shadow buffers for a DMA engine on the compute node for storing the message, each shadow buffer corresponding to a slot of an injection FIFO buffer maintained by the DMA engine; storing the message in the selected shadow buffer; creating a data descriptor for the message stored in the selected shadow buffer; injecting the datamore » « less
Full Text Available
Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

Patent Blocksome, Michael A.; Mamidala, Amith R.

Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic datamore » « less
Full Text Available
Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

Patent Blocksome, Michael A.; Mamidala, Amith R.

Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic datamore » « less
Full Text Available

Similar Records