Error recovery to enable error-free message transfer between nodes of a computer network

Blumrich, Matthias A.; Coteus, Paul W.; Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd; Steinmacher-Burow, Burkhard; Vranas, Pavlos M.

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Title: Error recovery to enable error-free message transfer between nodes of a computer network

Abstract

An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.

Inventors:: Blumrich, Matthias A.; Coteus, Paul W.; Chen, Dong; Gara, Alan; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd; Steinmacher-Burow, Burkhard; Vranas, Pavlos M.

Issue Date:: 2016-01-26

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1236465

Patent Number(s):: 9244759

Application Number:: 14/148,348

Assignee:: International Business Machines Corporation

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes
G06F11/1423 - {by reconfiguration of paths}
G06F9/46 - Multiprogramming arrangements

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L1/0061 - {Error detection codes}
H04L1/08 - by repeating transmission, e.g. Verdan system {
H04L1/1607 - {Details of the supervisory signal}
H04L1/1867 - {Arrangements specific to the transmitter end}
H04L2001/0093 - {Point-to-multipoint}
H04L2001/0097 - {Relays}

Show less

DOE Contract Number:: B517552

Resource Type:: Patent

Resource Relation:: Patent File Date: 2014 Jan 06

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING; 99 GENERAL AND MISCELLANEOUS

Citation Formats


                    Blumrich, Matthias A., Coteus, Paul W., Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd, Steinmacher-Burow, Burkhard, and Vranas, Pavlos M. Error recovery to enable error-free message transfer between nodes of a computer network.  United States: N. p., 2016. 
        Web.

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                    Blumrich, Matthias A., Coteus, Paul W., Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd, Steinmacher-Burow, Burkhard, & Vranas, Pavlos M. Error recovery to enable error-free message transfer between nodes of a computer network.  United States.

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                    Blumrich, Matthias A., Coteus, Paul W., Chen, Dong, Gara, Alan, Giampapa, Mark E., Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd, Steinmacher-Burow, Burkhard, and Vranas, Pavlos M. Tue .  
        "Error recovery to enable error-free message transfer between nodes of a computer network".  United States.  https://www.osti.gov/servlets/purl/1236465.

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@article{osti_1236465,

  title        = {Error recovery to enable error-free message transfer between nodes of a computer network},

  author       = {Blumrich, Matthias A. and Coteus, Paul W. and Chen, Dong and Gara, Alan and Giampapa, Mark E. and Heidelberger, Philip and Hoenicke, Dirk and Takken, Todd and Steinmacher-Burow, Burkhard and Vranas, Pavlos M.},

  abstractNote = {An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2016},

  month        = {1}

}

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Similar Records

Title: Error recovery to enable error-free message transfer between nodes of a computer network

Abstract

Citation Formats

Packet switch network protocol patent, August 1989

Negotiation protocol for establishment of full duplex communication on a token ring network patent, May 1995

Reducing the complexities of the transmission control protocol for a high-speed networking environment patent, August 1995

Barrier and eureka synchronization architecture for multiprocessors patent, February 1998

Self-synchronous packet scrambler patent, November 1998

Method and apparatus for dynamically shifting between routing and switching packets in a transmission network patent, April 1999

Multi-protocol dual fiber link laser diode controller and method patent, September 1999

Distributed precomputation of network signal paths with table-based link capacity control patent, February 2000

Apparatus and method for improved vector processing to support extended-length integer arithmetic patent, September 2001

Architecture for lightweight signaling in ATM networks patent, April 2003

Global interrupt and barrier networks patent, October 2008

Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks patent, March 2010

Interfacing apparatus and method for adapting Ethernet directly to physical channel patent-application, November 2001

Method and computer program product for internet protocol (IP)-flow classification in a wireless point to multi-point (PTMP) patent-application, April 2003

Global interrupt and barrier networks patent-application, April 2004

Arithmetic functions in torus and tree networks patent-application, April 2004

Global tree network for computing structures patent-application, April 2004

Class network routing patent-application, April 2004

Novel massively parallel supercomputer patent-application, May 2004

Deterministic error recovery protocol patent-application, April 2005

Method and apparatus for universal data exchange gateway patent-application, November 2006

Method and system for communicating an information packet through multiple networks patent-application, March 2007

Packet switch network protocol
patent, August 1989

Negotiation protocol for establishment of full duplex communication on a token ring network
patent, May 1995

Reducing the complexities of the transmission control protocol for a high-speed networking environment
patent, August 1995

Barrier and eureka synchronization architecture for multiprocessors
patent, February 1998

Self-synchronous packet scrambler
patent, November 1998

Method and apparatus for dynamically shifting between routing and switching packets in a transmission network
patent, April 1999

Multi-protocol dual fiber link laser diode controller and method
patent, September 1999

Distributed precomputation of network signal paths with table-based link capacity control
patent, February 2000

Apparatus and method for improved vector processing to support extended-length integer arithmetic
patent, September 2001

Architecture for lightweight signaling in ATM networks
patent, April 2003

Global interrupt and barrier networks
patent, October 2008

Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks
patent, March 2010

Interfacing apparatus and method for adapting Ethernet directly to physical channel
patent-application, November 2001

Method and computer program product for internet protocol (IP)-flow classification in a wireless point to multi-point (PTMP)
patent-application, April 2003

Global interrupt and barrier networks
patent-application, April 2004

Arithmetic functions in torus and tree networks
patent-application, April 2004

Global tree network for computing structures
patent-application, April 2004

Class network routing
patent-application, April 2004

Novel massively parallel supercomputer
patent-application, May 2004

Deterministic error recovery protocol
patent-application, April 2005

Method and apparatus for universal data exchange gateway
patent-application, November 2006

Method and system for communicating an information packet through multiple networks
patent-application, March 2007