Title: Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Abstract

A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Inventors:

Asaad, Sameth W.; Kapur, Mohit

Issue Date:

2016-01-05

Research Org.:

International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1234684

Patent Number(s):

9230046

Application Number:

13/435,614

Assignee:

International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F30/331 - with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F9/455 - Emulation

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DOE Contract Number:  

B554331

Resource Type:

Patent

Resource Relation:

Patent File Date: 2012 Mar 30

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING