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Title: Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

Abstract

A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1234684
Patent Number(s):
9,230,046
Application Number:
13/435,614
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012 Mar 30
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Asaad, Sameth W., and Kapur, Mohit. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator. United States: N. p., 2016. Web.
Asaad, Sameth W., & Kapur, Mohit. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator. United States.
Asaad, Sameth W., and Kapur, Mohit. Tue . "Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator". United States. https://www.osti.gov/servlets/purl/1234684.
@article{osti_1234684,
title = {Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator},
author = {Asaad, Sameth W. and Kapur, Mohit},
abstractNote = {A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2016},
month = {1}
}

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Works referenced in this record:

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
conference, January 2012

  • Asaad, Sameh; Tierno, José; Bellofatto, Ralph
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