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Title: Detecting and correcting hard errors in a memory array

Abstract

Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.

Inventors:
; ; ; ;
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1226236
Patent Number(s):
9189326
Application Number:
14/048,830
Assignee:
Advanced Micro Devices, Inc.
Patent Classifications (CPCs):
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
AC52-07NA27344
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 Oct 08
Country of Publication:
United States
Language:
English
Subject:
96 KNOWLEDGE MANAGEMENT AND PRESERVATION

Citation Formats

Kalamatianos, John, John, Johnsy Kanjirapallil, Gelinas, Robert, Sridharan, Vilas K., and Nevius, Phillip E. Detecting and correcting hard errors in a memory array. United States: N. p., 2015. Web.
Kalamatianos, John, John, Johnsy Kanjirapallil, Gelinas, Robert, Sridharan, Vilas K., & Nevius, Phillip E. Detecting and correcting hard errors in a memory array. United States.
Kalamatianos, John, John, Johnsy Kanjirapallil, Gelinas, Robert, Sridharan, Vilas K., and Nevius, Phillip E. Thu . "Detecting and correcting hard errors in a memory array". United States. https://www.osti.gov/servlets/purl/1226236.
@article{osti_1226236,
title = {Detecting and correcting hard errors in a memory array},
author = {Kalamatianos, John and John, Johnsy Kanjirapallil and Gelinas, Robert and Sridharan, Vilas K. and Nevius, Phillip E.},
abstractNote = {Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {11}
}

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Works referenced in this record:

Low Vccmin fault-tolerant cache with highly predictable performance
conference, January 2009


ZerehCache: armoring cache architectures in high defect density technologies
conference, January 2009


Tolerating hard faults in microprocessor array structures
conference, January 2004