System, apparatus and methods to implement high-speed network analyzers

Title: System, apparatus and methods to implement high-speed network analyzers

Systems, apparatus and methods for the implementation of high-speed network analyzers are provided. A set of high-level specifications is used to define the behavior of the network analyzer emitted by a compiler. An optimized inline workflow to process regular expressions is presented without sacrificing the semantic capabilities of the processing engine. An optimized packet dispatcher implements a subset of the functions implemented by the network analyzer, providing a fast and slow path workflow used to accelerate specific processing units. Such dispatcher facility can also be used as a cache of policies, wherein if a policy is found, then packet manipulations associated with the policy can be quickly performed. An optimized method of generating DFA specifications for network signatures is also presented. The method accepts several optimization criteria, such as min-max allocations or optimal allocations based on the probability of occurrence of each signature input bit.

Inventors:: Ezick, James; Lethin, Richard; Ros-Giralt, Jordi; Szilagyi, Peter; Wohlford, David E

Issue Date:: 2015-11-10

OSTI Identifier:: 1225520

Assignee:: Reservoir Labs, Inc CHO

Patent Number(s):: 9,185,020

Application Number:: 12/770,649

Contract Number:: FG02-08ER85046

Resource Relation:: Patent File Date: 2010 Apr 29

Research Org:: Reservoir Labs, Inc. New York, NY(United States)

Sponsoring Org:: USDOE

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

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Other works cited in this record:

On the (Im)possibility of Obfuscating Programs
book, January 2001

Barak, Boaz; Goldreich, Oded; Impagliazzo, Rusell
Advances in Cryptology — CRYPTO 2001
DOI: 10.1007/3-540-44647-8_1

Putting Polyhedral Loop Transformations to Work
book, January 2004

Bastoul, Cédric; Cohen, Albert; Girbal, Sylvain
Languages and Compilers for Parallel Computing
p. 209-225
DOI: 10.1007/978-3-540-24644-2_14

(Pen)-ultimate tiling?
journal, August 1994

Boulet, Pierre; Darte, Alain; Risset, Tanguy
Integration, the VLSI Journal, Vol. 17, Issue 1, p. 33-51
DOI: 10.1016/0167-9260(94)90019-1

Flow-insensitive interprocedural alias analysis in the presence of pointers
book, June 2005

Burke, Michael; Carini, Paul; Choi, Jong-Deok
Languages and Compilers for Parallel Computing, p. 234-250
DOI: 10.1007/BFb0025882

Some efficient solutions to the affine scheduling problem. I. One-dimensional time
journal, October 1992

Feautrier, Paul
International Journal of Parallel Programming, Vol. 21, Issue 5, p. 313-347
DOI: 10.1007/BF01407835

Dataflow analysis of array and scalar references
journal, February 1991

Feautrier, Paul
International Journal of Parallel Programming, Vol. 20, Issue 1, p. 23-53
DOI: 10.1007/BF01407931

Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications
book, January 2001

Franke, Björn; O’Boyle, Michael; Goos, Gerhard
Compiler Construction
DOI: 10.1007/3-540-45306-7_6

Forward Communication Only Placements and Their Use for Parallel Program Construction
book, January 2005

Griebl, Martin; Feautrier, Paul; Größlinger, Armin
Languages and Compilers for Parallel Computing, p. 16-30
DOI: 10.1007/11596110_2

Space–time mapping and tiling: a helpful combination
journal, January 2004

Griebl, Martin; Faber, Peter; Lengauer, Christian
Concurrency and Computation: Practice and Experience, Vol. 16, Issue 23, p. 221-246
DOI: 10.1002/cpe.772

Precise Data Locality Optimization of Nested Loops
journal, January 2002

Loechner, Vincent; Meister, Benoit; Clauss, Philippe
The Journal of Supercomputing, Vol. 21, Issue 1, p. 37-76
DOI: 10.1023/A:1013535431127

Generation of Efficient Nested Loops from Polyhedra
journal, October 2000

Quillere, Fabien; Rajopadhye, Sanjay; Wilde, Doran
International Journal of Parallel Programming, Vol. 28, Issue 5, p. 469-498
DOI: 10.1023/A:1007554627716

The mapping of linear recurrence equations on regular arrays
journal, October 1989

Quinton, Patrice; van Dongen, Vincent
Journal of VLSI signal processing systems for signal, image and video technology, Vol. 1, Issue 2, p. 95-113
DOI: 10.1007/BF02477176

Adaptive array beamforming with fixed-point arithmetic matrix inversion using Givens rotations
conference, November 2001

Rabinkin, Daniel V.; Song, William; Vai, M. Michael
DOI: 10.1117/12.448661

Generation of high-performance protocol-aware analyzers with applications in intrusion detection systems
conference, April 2010

Ros-Giralt, Jordi; Szilagyi, Peter; Ezick, James
DOI: 10.1117/12.848702

A Compiler Framework for Tiling Imperfectly-Nested Loops
book, January 2000

Song, Yonghong; Li, Zhiyuan; Goos, Gerhard
Languages and Compilers for Parallel Computing
DOI: 10.1007/3-540-44905-1_12

Early Control of Register Pressure for Software Pipelined Loops
book, January 2003

Sid-Ahmed-Ali, Touati; Eisenbeis, Christine; Goos, Gerhard
Compiler Construction
DOI: 10.1007/3-540-36579-6_2

Polyhedral Code Generation in the Real World
book, January 2006

Vasilache, Nicolas; Bastoul, Cedric; Cohen, Albert
Compiler Construction, p. 185-201
DOI: 10.1007/11688839_16

An Efficient Inclusion-Based Points-To Analysis for Strictly-Typed Languages
book, January 2002

Whaley, John; Lam, Monica S.; Goos, Gerhard
Static Analysis
DOI: 10.1007/3-540-45789-5_15

Verifying safety properties of a class of infinite-state distributed algorithms
book, January 1995

Jonsson, Bengt; Kempe, Lars; Goos, Gerhard
Computer Aided Verification
DOI: 10.1007/3-540-60045-0_39

Parallel Sparse Supports for Array Intrinsic Functions of Fortran 90
journal, March 2001

Chang, Rong-Guey; Chuang, Tyng-Ruey; Lee, Jenq Kuen
The Journal of Supercomputing, Vol. 18, Issue 3, p. 305-339
DOI: 10.1023/A:1008113800183

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