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Title: Accelerating functional verification of an integrated circuit

Abstract

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Inventors:
; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1224431
Patent Number(s):
9,171,110
Application Number:
13/534,189
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012 Jun 27
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; 42 ENGINEERING

Citation Formats

Deindl, Michael, Ruedinger, Jeffrey Joseph, and Zoellin, Christian G. Accelerating functional verification of an integrated circuit. United States: N. p., 2015. Web.
Deindl, Michael, Ruedinger, Jeffrey Joseph, & Zoellin, Christian G. Accelerating functional verification of an integrated circuit. United States.
Deindl, Michael, Ruedinger, Jeffrey Joseph, and Zoellin, Christian G. Tue . "Accelerating functional verification of an integrated circuit". United States. https://www.osti.gov/servlets/purl/1224431.
@article{osti_1224431,
title = {Accelerating functional verification of an integrated circuit},
author = {Deindl, Michael and Ruedinger, Jeffrey Joseph and Zoellin, Christian G.},
abstractNote = {Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {10}
}

Patent:

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