Title: Semiconductive micro- and nano-wire array manufacturing

Abstract

The disclosure provides methods of manufacturing semiconductive structures using stamping and VLS techniques.

Inventors:

Warren, Emily L.; Audesirk, Heather A.; Lewis, Nathan S.

Issue Date:

2015-06-02

Research Org.:

California Institute of Technology (CalTech), Pasadena, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1183341

Patent Number(s):

9048097

Application Number:

13/972,809

Assignee:

California Institute of Technology (Pasadena, CA)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/0237 - {Materials}
H01L21/02381 - {Silicon, silicon germanium, germanium}
H01L21/02532 - {Silicon, silicon germanium, germanium}
H01L21/0259 - {Microstructure}
H01L21/02639 - {Preparation of substrate for selective deposition}
H01L21/02642 - {Mask materials other than SiO2 or SiN}
H01L21/02645 - {Seed materials}
H01L21/02653 - {Vapour-liquid-solid growth}
H01L21/02656 - {Special treatments}

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DOE Contract Number:  

FG02-05ER15754

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

14 SOLAR ENERGY; 36 MATERIALS SCIENCE; 77 NANOSCIENCE AND NANOTECHNOLOGY