Hardware based redundant multi-threading inside a GPU for improved reliability
Abstract
A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1179003
- Patent Number(s):
- 9026847
- Application Number:
- 13/724,968
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2012 Dec 21
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Sridharan, Vilas, and Gurumurthi, Sudhanva. Hardware based redundant multi-threading inside a GPU for improved reliability. United States: N. p., 2015.
Web.
Sridharan, Vilas, & Gurumurthi, Sudhanva. Hardware based redundant multi-threading inside a GPU for improved reliability. United States.
Sridharan, Vilas, and Gurumurthi, Sudhanva. Tue .
"Hardware based redundant multi-threading inside a GPU for improved reliability". United States. https://www.osti.gov/servlets/purl/1179003.
@article{osti_1179003,
title = {Hardware based redundant multi-threading inside a GPU for improved reliability},
author = {Sridharan, Vilas and Gurumurthi, Sudhanva},
abstractNote = {A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2015},
month = {5}
}
Works referenced in this record:
Control of multiple computer processes using a mutual exclusion primitive ordering mechanism
patent, December 2002
- Williams, Emrys J.
- US Patent Document 6,499,048
Methods and apparatus for fault-detecting and fault-tolerant process control
patent, May 2006
- Galpin, Samuel
- US Patent Document 7,043,728
Synchronous parallel pixel processing for scalable color reproduction systems
patent, July 2014
- Gnanasambandam, Shanmuga-Nathan; Mestha, Lalit Keshav
- US Patent Document 8,773,446