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Title: Register file soft error recovery

Abstract

Register file soft error recovery including a system that includes a first register file and a second register file that mirrors the first register file. The system also includes an arithmetic pipeline for receiving data read from the first register file, and error detection circuitry to detect whether the data read from the first register file includes corrupted data. The system further includes error recovery circuitry to insert an error recovery instruction into the arithmetic pipeline in response to detecting the corrupted data. The inserted error recovery instruction replaces the corrupted data in the first register file with a copy of the data from the second register file.

Inventors:
; ; ; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1176530
Patent Number(s):
8,560,924
Application Number:
12/652,360
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2010 Jan 05
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Fleischer, Bruce M., Fox, Thomas W., Wait, Charles D., Muff, Adam J., and Watson, III, Alfred T. Register file soft error recovery. United States: N. p., 2013. Web.
Fleischer, Bruce M., Fox, Thomas W., Wait, Charles D., Muff, Adam J., & Watson, III, Alfred T. Register file soft error recovery. United States.
Fleischer, Bruce M., Fox, Thomas W., Wait, Charles D., Muff, Adam J., and Watson, III, Alfred T. Tue . "Register file soft error recovery". United States. https://www.osti.gov/servlets/purl/1176530.
@article{osti_1176530,
title = {Register file soft error recovery},
author = {Fleischer, Bruce M. and Fox, Thomas W. and Wait, Charles D. and Muff, Adam J. and Watson, III, Alfred T.},
abstractNote = {Register file soft error recovery including a system that includes a first register file and a second register file that mirrors the first register file. The system also includes an arithmetic pipeline for receiving data read from the first register file, and error detection circuitry to detect whether the data read from the first register file includes corrupted data. The system further includes error recovery circuitry to insert an error recovery instruction into the arithmetic pipeline in response to detecting the corrupted data. The inserted error recovery instruction replaces the corrupted data in the first register file with a copy of the data from the second register file.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2013},
month = {10}
}

Patent:

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