skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Shared performance monitor in a multiprocessor system

Abstract

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Inventors:
; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1176464
Patent Number(s):
8230433
Application Number:
11/768,777
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Resource Type:
Patent
Resource Relation:
Patent File Date: 2007 Jun 26
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Chiu, George, Gara, Alan G., and Salapura, Valentina. Shared performance monitor in a multiprocessor system. United States: N. p., 2012. Web.
Chiu, George, Gara, Alan G., & Salapura, Valentina. Shared performance monitor in a multiprocessor system. United States.
Chiu, George, Gara, Alan G., and Salapura, Valentina. Tue . "Shared performance monitor in a multiprocessor system". United States. https://www.osti.gov/servlets/purl/1176464.
@article{osti_1176464,
title = {Shared performance monitor in a multiprocessor system},
author = {Chiu, George and Gara, Alan G. and Salapura, Valentina},
abstractNote = {A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2012},
month = {7}
}

Patent:

Save / Share:

Works referenced in this record:

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005


Performance evaluation of adaptive MPI
conference, January 2006

  • Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
  • https://doi.org/10.1145/1122971.1122976

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990


Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988


Overview of the Blue Gene/L system architecture
journal, March 2005


Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005


Intel 870: a building block for cost-effective, scalable servers
journal, March 2002


Blue Gene/L advanced diagnostics environment
journal, March 2005