Agile high resolution arbitrary waveform generator with jitterless frequency stepping
Abstract
Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.
- Inventors:
- Issue Date:
- Research Org.:
- Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1176292
- Patent Number(s):
- 7714623
- Application Number:
- 12/100,011
- Assignee:
- UT-Battelle, LLC (Oak Ridge, TN)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC05-00OR22725
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; 42 ENGINEERING; 97 MATHEMATICS AND COMPUTING
Citation Formats
Reilly, Peter T. A., and Koizumi, Hideya. Agile high resolution arbitrary waveform generator with jitterless frequency stepping. United States: N. p., 2010.
Web.
Reilly, Peter T. A., & Koizumi, Hideya. Agile high resolution arbitrary waveform generator with jitterless frequency stepping. United States.
Reilly, Peter T. A., and Koizumi, Hideya. Tue .
"Agile high resolution arbitrary waveform generator with jitterless frequency stepping". United States. https://www.osti.gov/servlets/purl/1176292.
@article{osti_1176292,
title = {Agile high resolution arbitrary waveform generator with jitterless frequency stepping},
author = {Reilly, Peter T. A. and Koizumi, Hideya},
abstractNote = {Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue May 11 00:00:00 EDT 2010},
month = {Tue May 11 00:00:00 EDT 2010}
}