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Title: DMA shared byte counters in a parallel computer

Abstract

A parallel computer system is constructed as a network of interconnected compute nodes. Each of the compute nodes includes at least one processor, a memory and a DMA engine. The DMA engine includes a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers. The injection FIFOs maintain memory locations of the injection FIFO metadata memory locations including its current head and tail, and the reception FIFOs maintain the reception FIFO metadata memory locations including its current head and tail. The injection byte counters and reception byte counters may be shared between messages.

Inventors:
; ; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1176223
Patent Number(s):
7694035
Application Number:
11/768,781
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Chen, Dong, Gara, Alan G., Heidelberger, Philip, and Vranas, Pavlos. DMA shared byte counters in a parallel computer. United States: N. p., 2010. Web.
Chen, Dong, Gara, Alan G., Heidelberger, Philip, & Vranas, Pavlos. DMA shared byte counters in a parallel computer. United States.
Chen, Dong, Gara, Alan G., Heidelberger, Philip, and Vranas, Pavlos. Tue . "DMA shared byte counters in a parallel computer". United States. https://www.osti.gov/servlets/purl/1176223.
@article{osti_1176223,
title = {DMA shared byte counters in a parallel computer},
author = {Chen, Dong and Gara, Alan G. and Heidelberger, Philip and Vranas, Pavlos},
abstractNote = {A parallel computer system is constructed as a network of interconnected compute nodes. Each of the compute nodes includes at least one processor, a memory and a DMA engine. The DMA engine includes a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers. The injection FIFOs maintain memory locations of the injection FIFO metadata memory locations including its current head and tail, and the reception FIFOs maintain the reception FIFO metadata memory locations including its current head and tail. The injection byte counters and reception byte counters may be shared between messages.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2010},
month = {4}
}

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