skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Size reduction techniques for vital compliant VHDL simulation models

Abstract

A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1175858
Patent Number(s):
7085701
Application Number:
10/038,311
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Rich, Marvin J., and Misra, Ashutosh. Size reduction techniques for vital compliant VHDL simulation models. United States: N. p., 2006. Web.
Rich, Marvin J., & Misra, Ashutosh. Size reduction techniques for vital compliant VHDL simulation models. United States.
Rich, Marvin J., and Misra, Ashutosh. Tue . "Size reduction techniques for vital compliant VHDL simulation models". United States. https://www.osti.gov/servlets/purl/1175858.
@article{osti_1175858,
title = {Size reduction techniques for vital compliant VHDL simulation models},
author = {Rich, Marvin J. and Misra, Ashutosh},
abstractNote = {A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2006},
month = {8}
}

Patent:

Save / Share:

Works referenced in this record:

Modeling ASIC memories in VHDL
conference, January 1996


OLIVIA: object oriented logic simulation implementing the VITAL standard
conference, January 1997


Standardizing ASIC libraries in VHDL using VITAL: a tutorial
conference, January 1995