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Title: Method and system for an on-chip AC self-test controller

Abstract

A method for performing AC self-test on an integrated circuit, including a system clock for use during normal operation. The method includes applying a long data capture pulse to a first test register in response to the system clock, and further applying at an speed data launch pulse to the first test register in response to the system clock. Inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register. Applying at speed data capture pulse to a second test register in response to the system clock. Inputting the output from the logic path to the second test register in response to applying the at speed data capture pulse to the second register. Applying a long data launch pulse to the second test register in response to the system clock.

Inventors:
; ;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1175784
Patent Number(s):
7,058,866
Application Number:
10/131,554
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Flanagan, John D., Herring, Jay R., and Lo, Tin-Chee. Method and system for an on-chip AC self-test controller. United States: N. p., 2006. Web.
Flanagan, John D., Herring, Jay R., & Lo, Tin-Chee. Method and system for an on-chip AC self-test controller. United States.
Flanagan, John D., Herring, Jay R., and Lo, Tin-Chee. Tue . "Method and system for an on-chip AC self-test controller". United States. https://www.osti.gov/servlets/purl/1175784.
@article{osti_1175784,
title = {Method and system for an on-chip AC self-test controller},
author = {Flanagan, John D. and Herring, Jay R. and Lo, Tin-Chee},
abstractNote = {A method for performing AC self-test on an integrated circuit, including a system clock for use during normal operation. The method includes applying a long data capture pulse to a first test register in response to the system clock, and further applying at an speed data launch pulse to the first test register in response to the system clock. Inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register. Applying at speed data capture pulse to a second test register in response to the system clock. Inputting the output from the logic path to the second test register in response to applying the at speed data capture pulse to the second register. Applying a long data launch pulse to the second test register in response to the system clock.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2006},
month = {6}
}

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