Redundant single event upset supression system

Hoff, James R.

Title: Redundant single event upset supression system

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Abstract

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Inventors:: Hoff, James R.

Issue Date:: 2006-04-04

Research Org.:: Universities Research Association, Inc., Washington, DC (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1175691

Patent Number(s):: 7023235

Application Number:: 10/735,489

Assignee:: Universities Research Association, Inc. (Washington, DC)

Patent Classifications (CPCs):: H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

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H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K3/0375 - {provided with means for increasing reliability
H03K19/00338 - {In field effect transistor circuits}

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C11/4125 - {Cells incorporating circuit means for protection against loss of information

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K19/00392 - {by circuit redundancy

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DOE Contract Number:: AC02-76CH03000

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY

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                    Hoff, James R. Redundant single event upset supression system.  United States: N. p., 2006. 
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                    Hoff, James R. Redundant single event upset supression system.  United States.

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                    Hoff, James R. Tue .  
        "Redundant single event upset supression system".  United States.  https://www.osti.gov/servlets/purl/1175691.

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@article{osti_1175691,

  title        = {Redundant single event upset supression system},

  author       = {Hoff, James R.},

  abstractNote = {CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2006},

  month        = {4}

}

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