Single-transistor-clocked flip-flop

Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

Title: Single-transistor-clocked flip-flop

Abstract

The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Inventors:: Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

Issue Date:: 2005-08-30

Research Org.:: University of Louisiana at Lafayette, Lafayette, LA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1175478

Patent Number(s):: 6937079

Application Number:: 10/628,737

Assignee:: University of Louisiana at Lafayette (Lafayette, LA)

Patent Classifications (CPCs):: H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE

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H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H03K3/356156 - {with synchronous operation}

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DOE Contract Number:: 97ER12220

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

Citation Formats


                    Zhao, Peiyi, Darwish, Tarek, and Bayoumi, Magdy. Single-transistor-clocked flip-flop.  United States: N. p., 2005. 
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                    Zhao, Peiyi, Darwish, Tarek, & Bayoumi, Magdy. Single-transistor-clocked flip-flop.  United States.

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                    Zhao, Peiyi, Darwish, Tarek, and Bayoumi, Magdy. Tue .  
        "Single-transistor-clocked flip-flop".  United States.  https://www.osti.gov/servlets/purl/1175478.

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@article{osti_1175478,

  title        = {Single-transistor-clocked flip-flop},

  author       = {Zhao, Peiyi and Darwish, Tarek and Bayoumi, Magdy},

  abstractNote = {The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2005},

  month        = {8}

}

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Works referenced in this record:

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
journal, May 1998

Kawaguchi, H.; Sakurai, T.
IEEE Journal of Solid-State Circuits, Vol. 33, Issue 5
https://doi.org/10.1109/4.668997

High-speed CMOS circuit technique
journal, February 1989

Yuan, J.; Svensson, C.
IEEE Journal of Solid-State Circuits, Vol. 24, Issue 1
https://doi.org/10.1109/4.16303

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
journal, September 2007

Heo, S.; Krashinsky, R.; Asanovic, K.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, Issue 9
https://doi.org/10.1109/TVLSI.2007.902211

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors
conference, January 2001

Tschanz, James; Narendra, Siva; Chen, Zhanping
Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01
https://doi.org/10.1145/383082.383121

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
journal, April 1999

Stojanovic, V.; Oklobdzija, V. G.
IEEE Journal of Solid-State Circuits, Vol. 34, Issue 4
https://doi.org/10.1109/4.753687

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Similar Records

Title: Single-transistor-clocked flip-flop

Abstract

Citation Formats

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction journal, May 1998

High-speed CMOS circuit technique journal, February 1989

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy journal, September 2007

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors conference, January 2001

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems journal, April 1999

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
journal, May 1998

High-speed CMOS circuit technique
journal, February 1989

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
journal, September 2007

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors
conference, January 2001

Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
journal, April 1999