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Title: Single-transistor-clocked flip-flop

Abstract

The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Inventors:
; ;
Issue Date:
Research Org.:
University of Louisiana at Lafayette, Lafayette, LA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1175478
Patent Number(s):
6937079
Application Number:
10/628,737
Assignee:
University of Louisiana at Lafayette (Lafayette, LA)
Patent Classifications (CPCs):
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
DOE Contract Number:  
97ER12220
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Zhao, Peiyi, Darwish, Tarek, and Bayoumi, Magdy. Single-transistor-clocked flip-flop. United States: N. p., 2005. Web.
Zhao, Peiyi, Darwish, Tarek, & Bayoumi, Magdy. Single-transistor-clocked flip-flop. United States.
Zhao, Peiyi, Darwish, Tarek, and Bayoumi, Magdy. Tue . "Single-transistor-clocked flip-flop". United States. https://www.osti.gov/servlets/purl/1175478.
@article{osti_1175478,
title = {Single-transistor-clocked flip-flop},
author = {Zhao, Peiyi and Darwish, Tarek and Bayoumi, Magdy},
abstractNote = {The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2005},
month = {8}
}

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Works referenced in this record:

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
journal, May 1998


High-speed CMOS circuit technique
journal, February 1989


Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
journal, September 2007


Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors
conference, January 2001


Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
journal, April 1999