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Title: Delay correlation analysis and representation for vital complaint VHDL models

Abstract

A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.

Inventors:
;
Issue Date:
Research Org.:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1175126
Patent Number(s):
6817000
Application Number:
10/038,209
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Rich, Marvin J., and Misra, Ashutosh. Delay correlation analysis and representation for vital complaint VHDL models. United States: N. p., 2004. Web.
Rich, Marvin J., & Misra, Ashutosh. Delay correlation analysis and representation for vital complaint VHDL models. United States.
Rich, Marvin J., and Misra, Ashutosh. Tue . "Delay correlation analysis and representation for vital complaint VHDL models". United States. https://www.osti.gov/servlets/purl/1175126.
@article{osti_1175126,
title = {Delay correlation analysis and representation for vital complaint VHDL models},
author = {Rich, Marvin J. and Misra, Ashutosh},
abstractNote = {A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2004},
month = {11}
}

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Works referenced in this record:

Modeling ASIC memories in VHDL
conference, January 1996


OLIVIA: object oriented logic simulation implementing the VITAL standard
conference, January 1997