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Title: Silicon on insulator self-aligned transistors

Abstract

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Inventors:
Issue Date:
Research Org.:
Univ. of California, Oakland, CA (United States); Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1174590
Patent Number(s):
6649977
Application Number:
08/526,339
Assignee:
The Regents of the University of California (Oakland, CA)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Citation Formats

McCarthy, Anthony M. Silicon on insulator self-aligned transistors. United States: N. p., 2003. Web.
McCarthy, Anthony M. Silicon on insulator self-aligned transistors. United States.
McCarthy, Anthony M. Tue . "Silicon on insulator self-aligned transistors". United States. https://www.osti.gov/servlets/purl/1174590.
@article{osti_1174590,
title = {Silicon on insulator self-aligned transistors},
author = {McCarthy, Anthony M.},
abstractNote = {A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2003},
month = {11}
}

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Works referenced in this record:

Vertically structured silicon membrane by electrochemical etching
journal, April 1990


Ellipsometric Study of the Etch‐Stop Mechanism in Heavily Doped Silicon
journal, January 1985


Study of electrochemical etch-stop for high-precision thickness control of silicon membranes
journal, April 1989