Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems
Abstract
Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.
- Inventors:
- Issue Date:
- Research Org.:
- ~Individually Owned Patent
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1174501
- Patent Number(s):
- 6624493
- Application Number:
- 09/716,046
- Assignee:
- Welch, James D.
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- FG47-93R701314
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 47 OTHER INSTRUMENTATION
Citation Formats
Welch, James D. Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems. United States: N. p., 2003.
Web.
Welch, James D. Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems. United States.
Welch, James D. Tue .
"Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems". United States. https://www.osti.gov/servlets/purl/1174501.
@article{osti_1174501,
title = {Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems},
author = {Welch, James D.},
abstractNote = {Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2003},
month = {9}
}
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