Title: Processes for multi-layer devices utilizing layer transfer

Abstract

A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.

Inventors:

Nielson, Gregory N; Sanchez, Carlos Anthony; Tauke-Pedretti, Anna; Kim, Bongsang; Cederberg, Jeffrey; Okandan, Murat; Cruz-Campa, Jose Luis; Resnick, Paul J

Issue Date:

Tue Feb 03 00:00:00 EST 2015

Research Org.:

Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1169088

Patent Number(s):

8946052

Application Number:

13/627,425

Assignee:

Sandia Corporation (Albuquerque, NM)

Patent Classifications (CPCs):

B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81C - PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81C - PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS

B81C1/00373 - {Selective deposition, e.g. printing or microcontact printing}
B81C2201/0194 - the layer being structured

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/283 - Deposition of conductive or insulating materials for electrodes {conducting electric current}
H01L21/31111 - {by chemical means}
H01L21/561 - {Batch processing}
H01L21/568 - {Temporary substrate used as encapsulation process aid
H01L21/6835 - {using temporarily an auxiliary support}
H01L21/6836 - {Wafer tapes, e.g. grinding or dicing support tapes
H01L2221/68327 - used during dicing or grinding
H01L2221/68354 - used to support diced chips prior to mounting
H01L2221/68368 - used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
H01L2221/68381 - Details of chemical or physical process used for separating the auxiliary support from a device or wafer
H01L2224/0401 - Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L2224/08145 - the bodies being stacked
H01L2224/11 - Manufacturing methods
H01L2224/13005 - Structure
H01L2224/131 - with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
H01L2224/14135 - Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
H01L2224/80001 - by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
H01L2224/80006 - being a temporary or sacrificial substrate
H01L2224/80896 - between electrically insulating surfaces, e.g. oxide or nitride layers
H01L2224/9202 - Forming additional connectors after the connecting process
H01L2224/97 - the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
H01L2225/06517 - Bump or bump-like direct electrical connections from device to substrate
H01L2225/06568 - the devices decreasing in size, e.g. pyramidical stack
H01L24/13 - {of an individual bump connector}
H01L24/80 - {Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}
H01L24/97 - {the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting}
H01L25/0657 - {Stacked arrangements of devices}
H01L25/50 - {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
H01L2924/00012 - Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
H01L2924/014 - Solder alloys

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DOE Contract Number:  

AC04-94AL85000

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

42 ENGINEERING