Shared performance monitor in a multiprocessor system

Chiu, George; Gara, Alan G; Salapura, Valentina

Title: Shared performance monitor in a multiprocessor system

Abstract

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Inventors:: Chiu, George; Gara, Alan G; Salapura, Valentina

Issue Date:: 2014-12-02

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1164662

Patent Number(s):: 8904392

Application Number:: 13/484,797

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/3409 - {for performance assessment}
G06F2201/86 - Event-based monitoring
G06F2201/88 - Monitoring involving counting

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/348 - {Circuit details, i.e. tracer hardware}

Show less

DOE Contract Number:: B548850

Resource Type:: Patent

Resource Relation:: Patent File Date: 2012 May 31

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Chiu, George, Gara, Alan G, and Salapura, Valentina. Shared performance monitor in a multiprocessor system.  United States: N. p., 2014. 
        Web.

Copy to clipboard


                    Chiu, George, Gara, Alan G, & Salapura, Valentina. Shared performance monitor in a multiprocessor system.  United States.

Copy to clipboard


                    Chiu, George, Gara, Alan G, and Salapura, Valentina. Tue .  
        "Shared performance monitor in a multiprocessor system".  United States.  https://www.osti.gov/servlets/purl/1164662.

Copy to clipboard


                    
@article{osti_1164662,

  title        = {Shared performance monitor in a multiprocessor system},

  author       = {Chiu, George and Gara, Alan G and Salapura, Valentina},

  abstractNote = {A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {12}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Almási, George; Heidelberger, Philip; Archer, Charles J.
Proceedings of the 19th annual international conference on Supercomputing - ICS '05
https://doi.org/10.1145/1088149.1088183

Overview of the Blue Gene/L system architecture
journal, March 2005

Gara, A.; Blumrich, M. A.; Chen, D.
IBM Journal of Research and Development, Vol. 49, Issue 2.3
https://doi.org/10.1147/rd.492.0195

Performance evaluation of adaptive MPI
conference, January 2006

Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
https://doi.org/10.1145/1122971.1122976

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Chaiken, D.; Fields, C.; Kurihara, K.
Computer, Vol. 23, Issue 6
https://doi.org/10.1109/2.55500

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Dubois, M.; Scheurich, C.; Briggs, F. A.
Computer, Vol. 21, Issue 2
https://doi.org/10.1109/2.15

Blue Gene/L advanced diagnostics environment
journal, March 2005

Giampapa, M. E.; Bellofatto, R.; Blumrich, M. A.
IBM Journal of Research and Development, Vol. 49, Issue 2.3
https://doi.org/10.1147/rd.492.0319

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Briggs, F.; Cekleov, M.; Creta, K.
IEEE Micro, Vol. 22, Issue 2
https://doi.org/10.1109/MM.2002.997878

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005

Pande, P. P.; Grecu, C.; Jones, M.
IEEE Transactions on Computers, Vol. 54, Issue 8
https://doi.org/10.1109/TC.2005.134

Similar Records in DOE Patents and OSTI.GOV collections:

Reader set encoding for directory of shared cache memory in multiprocessor system

Patent Ahn, Dnaiel; Ceze, Luis H.; Gara, Alan; ...

In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.
Full Text Available
Programmable partitioning for high-performance coherence domains in a multiprocessor system

Patent Blumrich, Matthias A [Ridgefield, CT]; Salapura, Valentina [Chappaqua, NY]

A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units includes a local cache, and the snoop units are provided for supporting cache coherency in the multiprocessor system. Each of the snoop units is connected to a respective one of the processing units and to all of the other snoop units. The multiprocessor computing system further includes a partitioning system for using the snoop units to partition the multitude of processing units intomore » « less
Full Text Available
Real-time performance monitoring and management system

Patent Budhraja, Vikram S [Los Angeles, CA]; Dyer, James D [La Mirada, CA]; Martinez Morales, Carlos A [Upland, CA]

A real-time performance monitoring system for monitoring an electric power grid. The electric power grid has a plurality of grid portions, each grid portion corresponding to one of a plurality of control areas. The real-time performance monitoring system includes a monitor computer for monitoring at least one of reliability metrics, generation metrics, transmission metrics, suppliers metrics, grid infrastructure security metrics, and markets metrics for the electric power grid. The data for metrics being monitored by the monitor computer are stored in a data base, and a visualization of the metrics is displayed on at least one display computer having amore » « less
Full Text Available
Performing an allreduce operation using shared memory

Patent Archer, Charles J; Dozsa, Gabor; Ratterman, Joseph D; ...

Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing,more » « less
Full Text Available
Performing an allreduce operation using shared memory

Patent Archer, Charles J [Rochester, MN]; Dozsa, Gabor [Ardsley, NY]; Ratterman, Joseph D [Rochester, MN]; ...

Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing,more » « less
Full Text Available

Similar Records

Title: Shared performance monitor in a multiprocessor system

Abstract

Citation Formats

Optimization of MPI collective communication on BlueGene/L systems conference, January 2005

Overview of the Blue Gene/L system architecture journal, March 2005

Performance evaluation of adaptive MPI conference, January 2006

Directory-based cache coherence in large-scale multiprocessors journal, June 1990

Synchronization, coherence, and event ordering in multiprocessors journal, February 1988

Blue Gene/L advanced diagnostics environment journal, March 2005

Intel 870: a building block for cost-effective, scalable servers journal, March 2002

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal, August 2005

Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005

Overview of the Blue Gene/L system architecture
journal, March 2005

Performance evaluation of adaptive MPI
conference, January 2006

Directory-based cache coherence in large-scale multiprocessors
journal, June 1990

Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988

Blue Gene/L advanced diagnostics environment
journal, March 2005

Intel 870: a building block for cost-effective, scalable servers
journal, March 2002

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005