Shared performance monitor in a multiprocessor system
Abstract
A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1164662
- Patent Number(s):
- 8904392
- Application Number:
- 13/484,797
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- B548850
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2012 May 31
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Chiu, George, Gara, Alan G, and Salapura, Valentina. Shared performance monitor in a multiprocessor system. United States: N. p., 2014.
Web.
Chiu, George, Gara, Alan G, & Salapura, Valentina. Shared performance monitor in a multiprocessor system. United States.
Chiu, George, Gara, Alan G, and Salapura, Valentina. Tue .
"Shared performance monitor in a multiprocessor system". United States. https://www.osti.gov/servlets/purl/1164662.
@article{osti_1164662,
title = {Shared performance monitor in a multiprocessor system},
author = {Chiu, George and Gara, Alan G and Salapura, Valentina},
abstractNote = {A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {12}
}
Works referenced in this record:
Apparatus for transferring blocks of information from one node to a second node in a computer network
patent, October 1988
- Strecker, William D.; Stewart, Robert E.; Fuller, Samuel
- US Patent Document 4,777,595
Flow control for high speed networks
patent, November 1991
- Barzilai, Tsipora; Chen, Mon-Song; Kadaba, Bharath
- US Patent Document 5,063,562
Dual channel helical recorder
patent, August 1992
- Zook, Christopher P.; Bordasch, Robert; Georgis, Steven P.
- US Patent Document 5,142,422
Multiple clock rate test apparatus for testing digital systems
patent, September 1994
- Nadeau-Dostie, Benoit; Hassan, Abu; Burek, Dwayne
- US Patent Document 5,349,587
Partition control circuit for separately controlling message sending of nodes of tree-shaped routing network to divide the network into a number of partitions
patent, October 1994
- Douglas, David C.; Earls, John J.; Hillis, W. Daniel
- US Patent Document 5,353,412
Partially resettable, segmented DMA counter
patent, September 1995
- Macachor, Edgar R.
- US Patent Document 5,452,432
Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems
patent, June 1996
- Verma, Deepak; Potts, W. Henry
- US Patent Document 5,524,220
Event driven interface having a dynamically reconfigurable counter for monitoring a high speed data network according to changing traffic events
patent, March 1997
- Waclawsky, John G.; Hershey, Paul C.
- US Patent Document 5,615,135
Independent computer storage addressing in input/output transfers
patent, May 1997
- Calta, Salvatore A.; Cook, Robert Bryan; Luiz, Fernando A.
- US Patent Document 5,634,007
Cache coherency method and system employing serially encoded snoop responses
patent, August 1997
- Sherman, Kevin; Derrick, John Edward
- US Patent Document 5,659,710
Multimedia system and method of controlling data transfer between a host system and a network adapter using a DMA engine
patent, January 1998
- Graziano, Michael J.; Hauris, Jon F.; Stanley, Daniel L.
- US Patent Document 5,708,779
System and method for transmission rate control in a segmentation and reassembly (SAR) circuit under ATM protocol
patent, August 1998
- Miller, Michael J.; Murtaza, Bilal; Sun, Chih-Ping
- US Patent Document 5,796,735
Circuit for controlling access to a common memory based on priority
patent, September 1998
- Watanabe, Koichi; Machida, Hironobu; Sasama, Kazuo
- US Patent Document 5,809,278
Credit-based flow control checking and correction system
patent, October 1998
- Barkey, Kathy Sue; Bender, Carl A.; Garmire, Derrick LeRoy
- US Patent Document 5,825,748
Disk drive with cache controlled adaptively for amount of prefetch
patent, March 1999
- Sokolov, Daniel John; Swatosh, Timothy
- US Patent Document 5,890,211
ATM reassembly controller and method
patent, June 1999
- Thompson, Derek A.
- US Patent Document 5,917,828
Message transfer apparatus for controlling a message send in a packet switched interconnection network
patent, February 2000
- Moh, Sang Man; Shin, Sang Seok; Yoon, Suk Han
- US Patent Document 6,023,732
Reconstruction engine for a hardware circuit emulator
patent, May 2000
- Marantz, Joshua D.; Selvidge, Charley; Crouch, Ken
- US Patent Document 6,061,511
Multi-tasking adapter for parallel network applications
patent, June 2000
- Feeney, James William; Olnowich, Howard Thomas; Wilhelm, Jr., George William
- US Patent Document 6,072,781
Performance counters controlled by programmable logic
patent, August 2000
- Jouppi, Norman Paul; McCormack, Joel J.; Seiler, Larry
- US Patent Document 6,112,318
Method and system for optimizing write combining performance in a shared buffer structure
patent, September 2000
- Palanca, Salvador; Pentkovski, Vladimir; Cooray, Niranjan L.
- US Patent Document 6,122,715
Use of code vectors for frame forwarding in a bridge/router
patent, February 2001
- Schwartz, Leonard; Flanders, John A.; Townsend, William D.
- US Patent Document 6,185,214
Mechanism for delivering interrupt messages
patent, July 2001
- Wu, William S.; Azimi, Mani; Pawlowski, Stephen S.
- US Patent Document 6,263,397
Shared memory apparatus and method for multiprocessor systems
patent, September 2001
- Scardamalia, Theodore G.; West, Lynn P.
- US Patent Document 6,295,571
Bus arbitration system having both round robin and daisy chain arbiters
patent, October 2001
- Min, Kyung Pa; Lee, Gye Hun
- US Patent Document 6,311,249
Synchronous parallel system for emulation and discrete event simulation
patent, November 2001
- Steinman, Jeffrey S.
- US Patent Document 6,324,495
Active termination in a multidrop memory system
patent, March 2002
- Greeff, Roy; Lee, Terry R.; Harrison, Ron
- US Patent Document 6,356,106
Write combining buffer that supports snoop request
patent, April 2002
- Carmean, Douglas M.; Lince, Brent E.
- US Patent Document 6,366,984
Credit-based scheme for high performance communication between devices in a packet-based communication system
patent, August 2002
- O'Neill, Eugene; Quinlan, Una; O'Connell, Anne
- US Patent Document 6,442,162
Programmable architecture for visualizing sampled and geometry data
patent, October 2002
- Pfister, Hanspeter; Kreeger, Kevin; Marks, Joseph
- US Patent Document 6,466,227
System and method for scheduling traffic for different classes of service
patent, July 2003
- Chard, Gary F.; Utley, Robert Haskell
- US Patent Document 6,594,234
Snoop filter line replacement for reduction of back invalidates in multi-node architectures
patent, July 2003
- Anderson, James R.; Jayasimha, Doddaballapur N.
- US Patent Document 6,598,123
Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis
patent, July 2003
- Arimilli, Ravi Kumar; Dodson, John Steven; Fields, Jr., James Stephen
- US Patent Document 6,601,144
Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed
patent, October 2003
- Morioka, Michio; Kurosawa, Kenichi; Nakamikawa, Tetsuaki
- US Patent Document 6,631,447
Architecture for transport of multiple services in connectionless packet-based communication networks
patent, November 2003
- Bannai, Vinay K.; Barry, Charles F.; Choi, Inwhan
- US Patent Document 6,647,428
Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up
patent, December 2003
- Salmon, Joe; Volk, Andrew M.
- US Patent Document 6,662,305
Hierarchical selection of direct and indirect counting events in a performance monitor unit
patent, April 2004
- Davidson, Joel Roger; Laurens, Judith E. K.; Mericas, Alexander Erik
- US Patent Document 6,718,403
Method and systems for flow control of transmissions over channel-based switched fabric connections
patent, May 2004
- Hefty, Mark S.; Coffman, Jerrie L.
- US Patent Document 6,735,174
Performance monitoring based on instruction sampling in a microprocessor
patent, June 2004
- Gregoire, Dennis G.; Mericas, Alexander Erik; Tendler, Joel M.
- US Patent Document 6,748,522
Automatic byte swap and alignment for descriptor-based direct memory access data transfers
patent, September 2004
- Wang, Yi-Wen
- US Patent Document 6,799,232
Method for delivering packet boundary or other metadata to and from a device using direct memory controller
patent, May 2005
- Stadler, Laurent F.
- US Patent Document 6,889,266
Method and system for operation of a resilient closed communication network without a dedicated protection network segment
patent, May 2005
- Hashimoto, Noriaki
- US Patent Document 6,894,978
Multiple-capture DFT system for scan-based integrated circuits
patent, October 2005
- Wang, Laung-Terng; Lin, Meng-Chyi; Wen, Xiaoqing
- US Patent Document 6,954,887
Single-step processing and selecting debugging modes
patent, January 2006
- Roth, Charles P.; Singh, Ravi P.; Dingh, Tien
- US Patent Document 6,986,026
Binary tree arbitration system and method using embedded logic structure for controlling flag direction in multi-level arbiter node
patent, February 2006
- Golla, Prasad; Damm, Gerard; Ozugur, Timochin
- US Patent Document 7,007,123
System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment
patent, June 2006
- Fung, Henry T.
- US Patent Document 7,058,826
Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system
patent, June 2006
- Ripy, Paul B.; Chung, Keith; Geerdes, Gary
- US Patent Document 7,065,594
Multilevel fair priority round robin arbiter
patent, November 2006
- Chaudhari, Sunil; Liu, Jonathan W.; Patel, Manan
- US Patent Document 7,143,219
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
patent, March 2007
- Wang, Laung-Terng; Chang, Ming-Tung; Lin, Shyh-Horng
- US Patent Document 7,191,373
Memory array with precharge control circuit
patent, July 2007
- Liu, Yichiuh
- US Patent Document 7,239,565
Token-based active queue management
patent, October 2007
- Jeffries, Clark Debs; Kind, Andreas; Metzler, Bernard
- US Patent Document 7,280,477
Method and system for reassembling and parsing packets in a network environment
patent, November 2007
- de la Iglesia, Erik; Gomez, Miguel; Puri, Rahoul
- US Patent Document 7,298,746
Method, system, and program for remote resource management
patent, April 2008
- Springer, James; Jarvis, Thomas Charles; Spear, Gail A.
- US Patent Document 7,363,629
Method and apparatus for weighted fair queuing
patent, May 2008
- Lyon, Norman A.
- US Patent Document 7,373,420
Count calibration for synchronous data transfer between clock domains
patent, July 2008
- Fischer, Timothy C.; Naffziger, Samuel D.; Patella, Benjamin J.
- US Patent Document 7,401,245
System and method for providing a thermal shutdown circuit with temperature warning flags
patent, November 2008
- Wong, Kern Wai
- US Patent Document 7,454,640
System powered from a local area network cable
patent, November 2008
- Connor, Patrick; Dubal, Scott P.
- US Patent Document 7,454,641
Transferring data in a parallel processing environment
patent, December 2008
- Wentzlaff, David
- US Patent Document 7,461,236
Method and apparatus for efficient performance monitoring of a large number of simultaneous events
patent, December 2008
- Gara, Alan; Gschwind, Michael K.; Salapura, Valentina
- US Patent Document 7,461,383
Word line driving circuit putting word line into one of high level, low level and high impedance
patent, December 2008
- Matsubara, Yasushi
- US Patent Document 7,463,529
Coupling integrated circuits in a parallel processing environment
patent, May 2009
- Wentzlaff, David; Ramey, Carl; Agarwal, Anant
- US Patent Document 7,539,845
Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
patent, November 2009
- Asaka, Toshiharu
- US Patent Document 7,613,971
Mapping memory in a parallel processing environment
patent, November 2009
- Wentzlaff, David; Mattina, Matthew; Agarwal, Anant
- US Patent Document 7,620,791
Managing power consumption of a graphic apparatus
patent, April 2010
- Oh, Jang Geun
- US Patent Document 7,698,581
Heterogeneous processor core systems for improved throughput
patent, August 2011
- Farkas, Keith; Jouppi, Norman Paul; Ranganathan, Parthasarathy
- US Patent Document 7,996,839
Network Router Integrated onto a Silicon Chip
patent-application, December 2001
- Rowett, Kevin J.; Collins, Crosswell C.; Buell, Eric R.
- US Patent Application 09/359055; 20010055323
Data synchronization for a test access port
patent-application, June 2002
- Roth, Charles P.; Singh, Ravi P.; Kolagotla, Ravi
- US Patent Application 09/738405; 20020078420
Method and system for servicing cache line in response to partial cache line request
patent-application, July 2002
- Bogin, Zohar; Harriman, David J.; Wirkus, Zdzislaw A.
- US Patent Application 09/752846; 20020087801
Method for maintaining cache coherency in software in a shared memory system
patent-application, July 2002
- Hunter, Jeff L.; Buser, Mark L.; Lee, Bruce W. C.
- US Patent Application 09/998330; 20020100020
Cluster-based aggregated switching technique (CAST) for routing data packets and information objects in computer networks
patent-application, September 2002
- Garci-Luna-Aceves, J. J.; Samanta, Arindam
- US Patent Application 09/945104; 20020129086
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
patent-application, September 2002
- Wang, Laung-Terng; Chang, Ming-Tung; Lin, Shyh-Horng
- US Patent Application 10/086214; 20020138801
Partitioned cache of multiple logical levels with adaptive reconfiguration based on multiple criteria
patent-application, October 2002
- Rodriguez, Jorge R.
- US Patent Application 10/005426; 20020156979
Demarcated digital content and method for creating and processing demarcated digital works
patent-application, December 2002
- Tadayon, Bijan; Nahidipour, Aram; Wang, Xin
- US Patent Application 09/867754; 20020184159
Hardware mechanism to improve performance in a multi-node computer system
patent-application, January 2003
- Farrell, Jeremy J.; Masuyama, Kazunori; Miryala, Sudheer
- US Patent Application 10/150276; 20030007457
Data processor
patent-application, February 2003
- Ishikawa, Makoto; Arakawa, Fumio
- US Patent Application 10/145761; 20030028749
Apparatus, method and computer system for reducing power consumption of a processor or processors upon occurrence of a failure condition affecting the processor or processors
patent-application, March 2003
- Tymchenko, Viktor Andrew
- US Patent Application 09/955007; 20030050714
Weighted fair queuing scheduler
patent-application, March 2003
- Tayyar, Haitham F.; Alnuweiri, Hussein
- US Patent Application 10/164591; 20030050954
ASIC BIST controller employing multiple clock domains
patent-application, April 2003
- Dorsey, Michael C.
- US Patent Application 09/976490; 20030074616
Distributed processing architecture with scalable processing layers
patent-application, June 2003
- Khan, Shoab Ahmad; Rahmatullah, Muhammad Mohsin
- US Patent Application 10/004753; 20030105799
Shared bypass bus structure
patent-application, August 2003
- Kapur, Suvansh K.; Cheng, Kai; Hoogland, Robert J.
- US Patent Application 10/358568; 20030163649
Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses
patent-application, September 2003
- Luick, David Arnold
- US Patent Application 10/098002; 20030177335
Method for verifying clock signal frequency of computer sound interface
patent-application, October 2003
- Tsai, Chun-Nan
- US Patent Application 10/109702;20030188053
Methods of transmitting data packets without exceeding a maximum queue time period and related devices
patent-application, December 2003
- Van Der Zee, Thomas Martinus; Nitert, Wilhelmus Gerhardus; Aberg, Jan
- US Patent Application 10/174840; 20030235202
Partially inclusive snoop filter
patent-application, January 2004
- Safranek, Robert J.; Cheng, Kai
- US Patent Application 10/186490; 20040003184
On chip network with independent logical and physical layers
patent-application, January 2004
- Walker, Gary A.; Garinger, Ned D.; Dorr, Martin L.
- US Patent Application 10/207588; 20040019730
Computer system implementing synchronized broadcast using timestamps
patent-application, February 2004
- Cypher, Robert F.; Wood, David A.; Hill, Mark D.
- US Patent Application 10/610009; 20040024925
Single-step processing and selecting debugging modes
patent-application, April 2004
- Roth, Charls P.; Singh, Ravi P.; Dinh, Tien
- US Patent Application 09/738649; 20040073780
Novel massively parallel supercomputer
patent-application, May 2004
- Blumrich, Matthias A.; Chen, Dong; Chiu, George L.
- US Patent Application 10/468993; 20040103218
Multi-level and multi-resolution bus arbitration
patent-application, October 2004
- Shenderovich, Georgiy
- US Patent Application 10/414310; 20040210694
Method and apparatus for local and distributed data memory access ("DMA") control
patent-application, December 2004
- Spencer, Thomas Vincent
- US Patent Application 10/452330; 20040243739
Outer-loop power control for wireless communication systems
patent-application, January 2005
- Malladi, Durga P.; Chen, Tao; Wei, Tongbin
- US Patent Application 10/756957; 20050007986
Multiprocessor node controller circuit and method
patent-application, March 2005
- Deneroff, Martin M.; Kaldani, Givargis G.; Koren, Yuval
- US Patent Application 10/868181; 20050053057
Flexible DMA descriptor support
patent-application, April 2005
- Malalur, Govind
- US Patent Application 10/993491; 20050076163
System and method for conflict responses in a cache coherency protocol with ordering point migration
patent-application, July 2005
- Steely, JR., Simon C.; Tierney, Gregory Edward; Van Doren, Stephen R.
- US Patent Application 10/761073; 20050160238
Tables with direct memory access descriptor lists for distributed direct memory access
patent-application, September 2005
- Ganapathy, Kumar; Kanapathippillai, Ruban; Shah, Saurin
- US Patent Application 11/036827; 20050216613
Synchronized storage providing multiple synchronization semantics
patent-application, November 2005
- Kissell, Kevin D.
- US Patent Application 10/954988; 20050251613
System, method and device for counter array for a loop detector
patent-application, November 2005
- Gat, Tal
- US Patent Application 10/849025; 20050262333
Ferroelectric memory device and read control method thereof
patent-application, December 2005
- Takashima, Daisaburo
- US Patent Application 10/403120; 20050270886
Memory controller
patent-application, December 2005
- Lakshmanamurthy, Sridhar; Oza, Alpesh B.; Verma, Rohit R.
- US Patent Application 10/860549; 20050273564
System and method for checking validity of data transmission
patent-application, March 2006
- Hsu, Chun-Pin
- US Patent Application 11/025557; 20060050737
Low latency coherency protocol for a multi-chip multiprocessor system
patent-application, April 2006
- Beukema, Bruce L.; Hoover, Russell D.; Kriegel, Jon K.
- US Patent Application 10/961751; 20060080513
System and method for analyzing information relating to network devices
patent-application, July 2006
- Korzeniowski, Richard W.
- US Patent Application 10/973085; 20060168170
DMA engine for protocol processing
patent-application, September 2006
- Alexander, Thomas; Quattromani, Marc Alan; Rekow, Alexander
- US Patent Application 11/373858; 20060206635
Count calibration for synchronous data transfer between clock domains
patent-application, November 2006
- Fischer, Timothy C.; Naffziger, Samuel; Patella, Benjamin J.
- US Patent Application 11/118600; 20060248367
Method and system for fast data access using a memory array
patent-application, March 2007
- Beat, Robert
- US Patent Application 11/598010; 20070055832
Device prestructured arrangement to allow selective monitoring of a data storage device
patent-application,
- Butt, Kevin Dale; Greco, Paul Merrill; Mojica, Arturo Avila
- US Patent Application 11/258761; 20070094455
Method and apparatus for striping message payload data over a network
patent-application, June 2007
- Kim, Chulho; Sivaram, Rajeev; Treumann, Richard R.
- US Patent Application 11/298322; 20070133536
Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
patent-application, July 2007
- Wang, Laung-Terng; Chang, Ming-Tung; Chao, Hao-Jan
- US Patent Application 11/603085; 20070168803
Queue manager having a multi-level arbitrator
patent-application, July 2007
- Rodriguez, Jose M.; Lim, Soon Chich
- US Patent Application 11/321199; 20070174529
Systems and methods for access port ICMP analysis
patent-application, August 2007
- Sherman, Troy H.; Dunsmore, Bradley Neil; McMenamy, Kevin ROy
- US Patent Application 11/361012; 20070195774
Performance Monitor Device, Data Collecting Method and Program for the Same
patent-application, February 2008
- Matsuzaki, Hidenori; Maeda, Seiji
- US Patent Application 11/733379; 20080040634
Event source management using a metadata-driven framework
patent-application, May 2008
- Chakravarty, Dipto; Choudhary, Usman; Gassner, John Paul
- US Patent Application 11/730493; 20080114873
Method, Apparatus, and Computer Program Product for a Cache Coherency Protocol State That Predicts Locations of Modified Memory Blocks
patent-application, June 2008
- Cantin, Jason Frederick; Kunkel, Steven R.
- US Patent Application 11/954742; 20080147987
System and Method for Reactive and Deliberative Service Level Management (SLM)
patent-application, August 2010
- Lewis, Lundy M.
- US Patent Application 12/752971; 20100218104
Optimization of MPI collective communication on BlueGene/L systems
conference, January 2005
- Almási, George; Heidelberger, Philip; Archer, Charles J.
- Proceedings of the 19th annual international conference on Supercomputing - ICS '05
Overview of the Blue Gene/L system architecture
journal, March 2005
- Gara, A.; Blumrich, M. A.; Chen, D.
- IBM Journal of Research and Development, Vol. 49, Issue 2.3
Performance evaluation of adaptive MPI
conference, January 2006
- Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
- Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06
Directory-based cache coherence in large-scale multiprocessors
journal, June 1990
- Chaiken, D.; Fields, C.; Kurihara, K.
- Computer, Vol. 23, Issue 6
Synchronization, coherence, and event ordering in multiprocessors
journal, February 1988
- Dubois, M.; Scheurich, C.; Briggs, F. A.
- Computer, Vol. 21, Issue 2
Blue Gene/L advanced diagnostics environment
journal, March 2005
- Giampapa, M. E.; Bellofatto, R.; Blumrich, M. A.
- IBM Journal of Research and Development, Vol. 49, Issue 2.3
Intel 870: a building block for cost-effective, scalable servers
journal, March 2002
- Briggs, F.; Cekleov, M.; Creta, K.
- IEEE Micro, Vol. 22, Issue 2
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
journal, August 2005
- Pande, P. P.; Grecu, C.; Jones, M.
- IEEE Transactions on Computers, Vol. 54, Issue 8
Works referencing / citing this record:
Shared performance monitor in a multiprocessor system
patent, December 2014
- Chiu, George Liang-Tai; Gara, Alan; Salapura, Valentina
- US Patent Document 8,904,392