Store-operate-coherence-on-value

Chen, Dong; Heidelberger, Philip; Kumar, Sameer; Ohmacht, Martin; Steinmacher-Burow, Burkhard

Title: Store-operate-coherence-on-value

Abstract

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

Inventors:: Chen, Dong; Heidelberger, Philip; Kumar, Sameer; Ohmacht, Martin; Steinmacher-Burow, Burkhard

Issue Date:: 2014-11-18

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1163975

Patent Number(s):: 8892824

Application Number:: 12/986,652

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0815 - Cache consistency protocols
G06F9/30043 - {LOAD or STORE instructions
G06F9/30072 - {to perform conditional operations, e.g. using guard}
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F9/3834 - {Maintaining memory consistency

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 Jan 07

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Store-operate-coherence-on-value.  United States: N. p., 2014. 
        Web.

Copy to clipboard


                    Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, & Steinmacher-Burow, Burkhard. Store-operate-coherence-on-value.  United States.

Copy to clipboard


                    Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Tue .  
        "Store-operate-coherence-on-value".  United States.  https://www.osti.gov/servlets/purl/1163975.

Copy to clipboard


                    
@article{osti_1163975,

  title        = {Store-operate-coherence-on-value},

  author       = {Chen, Dong and Heidelberger, Philip and Kumar, Sameer and Ohmacht, Martin and Steinmacher-Burow, Burkhard},

  abstractNote = {A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {11}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
patent, March 2003

Kruse, Robert; Milling, Philip E.
US Patent Document 6,529,990
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6529990

Method and system for maintaining cache coherence of distributed shared memory system
patent-application, October 2006

Sakamoto, Mariko
US Patent Application 11/214850; 20060230237
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060230237

Similar Records in DOE Patents and OSTI.GOV collections:

Partitioned key-value store with atomic memory operations

Patent Bent, John M.; Faibish, Sorin; Grider, Gary

A partitioned key-value store is provided that supports atomic memory operations. A server performs a memory operation in a partitioned key-value store by receiving a request from an application for at least one atomic memory operation, the atomic memory operation comprising a memory address identifier; and, in response to the atomic memory operation, performing one or more of (i) reading a client-side memory location identified by the memory address identifier and storing one or more key-value pairs from the client-side memory location in a local key-value store of the server; and (ii) obtaining one or more key-value pairs from themore » « less
Full Text Available
Store operation with conditional push of a tag value to a queue

Patent Heidelberger, Philip; Steinmacher-Burow, Burkhard

According to one embodiment, a method for a store operation with a conditional push of a tag value to a queue is provided. The method includes configuring a queue that is accessible by an application, setting a value at an address in a memory device including a memory and a controller, receiving a request for an operation using the value at the address and performing the operation. The method also includes the controller writing a result of the operation to the address, thus changing the value at the address, the controller determining if the result of the operation meets amore » « less
Full Text Available
Store operations to maintain cache coherence

Patent Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
Full Text Available
Store operations to maintain cache coherence

Patent Evangelinos, Constantinos; Nair, Ravi; Ohmacht, Martin

In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
Full Text Available
Key-value store with internal key-value storage interface

Patent Bent, John M.; Faibish, Sorin; Ting, Dennis P. J.; ...

A key-value store is provided having one or more key-value storage interfaces. A key-value store on at least one compute node comprises a memory for storing a plurality of key-value pairs; and an abstract storage interface comprising a software interface module that communicates with at least one persistent storage device providing a key-value interface for persistent storage of one or more of the plurality of key-value pairs, wherein the software interface module provides the one or more key-value pairs to the at least one persistent storage device in a key-value format. The abstract storage interface optionally processes one or moremore » « less
Full Text Available

Similar Records

Title: Store-operate-coherence-on-value

Abstract

Citation Formats

Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system patent, March 2003

Method and system for maintaining cache coherence of distributed shared memory system patent-application, October 2006

Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
patent, March 2003

Method and system for maintaining cache coherence of distributed shared memory system
patent-application, October 2006