Decoding and optimized implementation of SECDED codes over GF(q)
Abstract
A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a columnwise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.
 Inventors:
 Issue Date:
 Research Org.:
 Sandia National Lab. (SNLNM), Albuquerque, NM (United States)
 Sponsoring Org.:
 USDOE
 OSTI Identifier:
 1163972
 Patent Number(s):
 8892985
 Application Number:
 14/281,567
 Assignee:
 Sandia Corporation (Albuquerque, NM)
 Patent Classifications (CPCs):

H  ELECTRICITY H03  BASIC ELECTRONIC CIRCUITRY H03M  CODING
 DOE Contract Number:
 AC0494AL85000
 Resource Type:
 Patent
 Resource Relation:
 Patent File Date: 2014 May 19
 Country of Publication:
 United States
 Language:
 English
 Subject:
 97 MATHEMATICS AND COMPUTING
Citation Formats
Ward, H Lee, Ganti, Anand, and Resnick, David R. Decoding and optimized implementation of SECDED codes over GF(q). United States: N. p., 2014.
Web.
Ward, H Lee, Ganti, Anand, & Resnick, David R. Decoding and optimized implementation of SECDED codes over GF(q). United States.
Ward, H Lee, Ganti, Anand, and Resnick, David R. Tue .
"Decoding and optimized implementation of SECDED codes over GF(q)". United States. https://www.osti.gov/servlets/purl/1163972.
@article{osti_1163972,
title = {Decoding and optimized implementation of SECDED codes over GF(q)},
author = {Ward, H Lee and Ganti, Anand and Resnick, David R},
abstractNote = {A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a columnwise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {11}
}
Works referenced in this record:
Hmatrix for error correcting circuitry
patentapplication, July 2005
 Worley, James Leon; Murillo, Laurent
 US Patent Application 10/742627; 20050149833
SyndromeError Mapping Method for Decoding Linear and Cyclic Codes
patentapplication, January 2009
 Chang, Yaotsu
 US Patent Application 11/829327; 20090031193
Probabilistic LearningBased Decoding of Communication Signals
patentapplication, June 2011
 Lee, Daniel Chonghwan
 US Patent Application 12/634686; 20110138255
Efficient Detection of Errors in Associative Memory
patentapplication, May 2012
 BremlerBarr, Anat; Hay, David; Hendler, Danny
 US Patent Application 13/258457; 20120117431
LDPC Code Family for MillimeterWave Band Communications in a Wireless Network
patentapplication, September 2012
 AbuSurra, Shadi; Henige, Thomas M.; Pisek, Eran
 US Patent Application 13/306747; 20120240001
Error Correction Encoding Apparatus, Error Correction Decoding Apparatus, Nonvolatile Semiconductor Memory System, and Parity Check Matrix Generation Method
patentapplication, February 2013
 Uchikawa, Hironori
 US Patent Application 13/406808; 20130055050