Petaflops router

Baker, Zachary Kent; Power, John Fredrick; Tripp, Justin Leonard; Dunham, Mark Edward; Stettler, Matthew W; Jones, John Alexander

Title: Petaflops router

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Abstract

Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a petascale equivalent supercomputer. A PetaFlops Router may comprise one or more PetaFlops Nodes, which may be connected to each other and/or external data provider/consumers via a programmable crossbar switch external to the PetaFlops Node. Each PetaFlops Node has a FPGA and a programmable intra-FPGA crossbar switch that permits input and output variables to be configurably connected to various physical operators contained in the FPGA as desired by a user. This allows a user to specify the instruction set of the system on a per-application basis. Further, the intra-FPGA crossbar switch permits the output of one operation to be delivered as an input to a second operation. By configuring the external crossbar switch, the output of a first operation on a first PetaFlops Node may be used as the input for a second operation on a second PetaFlops Node. An embodiment may provide an ability for the system to recognize and generate pipelined functions. Streaming operators may be connected together at run-time and appropriately staged to allowmore » « less

Inventors:: Baker, Zachary Kent; Power, John Fredrick; Tripp, Justin Leonard; Dunham, Mark Edward; Stettler, Matthew W; Jones, John Alexander

Issue Date:: 2014-10-14

Research Org.:: Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1159953

Patent Number(s):: 8861517

Application Number:: 12/763,840

Assignee:: Los Alamos National Security, LLC (Los Alamos, NM)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F15/17343 - {wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

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DOE Contract Number:: AC52-06NA25396

Resource Type:: Patent

Resource Relation:: Patent File Date: 2010 Apr 20

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Baker, Zachary Kent, Power, John Fredrick, Tripp, Justin Leonard, Dunham, Mark Edward, Stettler, Matthew W, and Jones, John Alexander. Petaflops router.  United States: N. p., 2014. 
        Web.

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                    Baker, Zachary Kent, Power, John Fredrick, Tripp, Justin Leonard, Dunham, Mark Edward, Stettler, Matthew W, & Jones, John Alexander. Petaflops router.  United States.

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                    Baker, Zachary Kent, Power, John Fredrick, Tripp, Justin Leonard, Dunham, Mark Edward, Stettler, Matthew W, and Jones, John Alexander. Tue .  
        "Petaflops router".  United States.  https://www.osti.gov/servlets/purl/1159953.

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@article{osti_1159953,

  title        = {Petaflops router},

  author       = {Baker, Zachary Kent and Power, John Fredrick and Tripp, Justin Leonard and Dunham, Mark Edward and Stettler, Matthew W and Jones, John Alexander},

  abstractNote = {Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a petascale equivalent supercomputer. A PetaFlops Router may comprise one or more PetaFlops Nodes, which may be connected to each other and/or external data provider/consumers via a programmable crossbar switch external to the PetaFlops Node. Each PetaFlops Node has a FPGA and a programmable intra-FPGA crossbar switch that permits input and output variables to be configurably connected to various physical operators contained in the FPGA as desired by a user. This allows a user to specify the instruction set of the system on a per-application basis. Further, the intra-FPGA crossbar switch permits the output of one operation to be delivered as an input to a second operation. By configuring the external crossbar switch, the output of a first operation on a first PetaFlops Node may be used as the input for a second operation on a second PetaFlops Node. An embodiment may provide an ability for the system to recognize and generate pipelined functions. Streaming operators may be connected together at run-time and appropriately staged to allow data to flow through a series of functions. This allows the system to provide high throughput and parallelism when possible. The PetaFlops Router may implement the user desired instructions by appropriately configuring the intra-FPGA crossbar switch on each PetaFlops Node and the external crossbar switch.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {10}

}

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