Petaflops router
Abstract
Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a petascale equivalent supercomputer. A PetaFlops Router may comprise one or more PetaFlops Nodes, which may be connected to each other and/or external data provider/consumers via a programmable crossbar switch external to the PetaFlops Node. Each PetaFlops Node has a FPGA and a programmable intra-FPGA crossbar switch that permits input and output variables to be configurably connected to various physical operators contained in the FPGA as desired by a user. This allows a user to specify the instruction set of the system on a per-application basis. Further, the intra-FPGA crossbar switch permits the output of one operation to be delivered as an input to a second operation. By configuring the external crossbar switch, the output of a first operation on a first PetaFlops Node may be used as the input for a second operation on a second PetaFlops Node. An embodiment may provide an ability for the system to recognize and generate pipelined functions. Streaming operators may be connected together at run-time and appropriately staged to allowmore »
- Inventors:
- Issue Date:
- Research Org.:
- Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1159953
- Patent Number(s):
- 8861517
- Application Number:
- 12/763,840
- Assignee:
- Los Alamos National Security, LLC (Los Alamos, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC52-06NA25396
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2010 Apr 20
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Baker, Zachary Kent, Power, John Fredrick, Tripp, Justin Leonard, Dunham, Mark Edward, Stettler, Matthew W, and Jones, John Alexander. Petaflops router. United States: N. p., 2014.
Web.
Baker, Zachary Kent, Power, John Fredrick, Tripp, Justin Leonard, Dunham, Mark Edward, Stettler, Matthew W, & Jones, John Alexander. Petaflops router. United States.
Baker, Zachary Kent, Power, John Fredrick, Tripp, Justin Leonard, Dunham, Mark Edward, Stettler, Matthew W, and Jones, John Alexander. Tue .
"Petaflops router". United States. https://www.osti.gov/servlets/purl/1159953.
@article{osti_1159953,
title = {Petaflops router},
author = {Baker, Zachary Kent and Power, John Fredrick and Tripp, Justin Leonard and Dunham, Mark Edward and Stettler, Matthew W and Jones, John Alexander},
abstractNote = {Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a petascale equivalent supercomputer. A PetaFlops Router may comprise one or more PetaFlops Nodes, which may be connected to each other and/or external data provider/consumers via a programmable crossbar switch external to the PetaFlops Node. Each PetaFlops Node has a FPGA and a programmable intra-FPGA crossbar switch that permits input and output variables to be configurably connected to various physical operators contained in the FPGA as desired by a user. This allows a user to specify the instruction set of the system on a per-application basis. Further, the intra-FPGA crossbar switch permits the output of one operation to be delivered as an input to a second operation. By configuring the external crossbar switch, the output of a first operation on a first PetaFlops Node may be used as the input for a second operation on a second PetaFlops Node. An embodiment may provide an ability for the system to recognize and generate pipelined functions. Streaming operators may be connected together at run-time and appropriately staged to allow data to flow through a series of functions. This allows the system to provide high throughput and parallelism when possible. The PetaFlops Router may implement the user desired instructions by appropriately configuring the intra-FPGA crossbar switch on each PetaFlops Node and the external crossbar switch.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 14 00:00:00 EDT 2014},
month = {Tue Oct 14 00:00:00 EDT 2014}
}
Works referenced in this record:
Cascadable bus based crossbar switch in a programmable logic device
patent, July 2003
- Jones, Christopher W.; Wilton, Steven J. E.
- US Patent Document 6,590,417
Cascadable bus based crossbar switching in a programmable logic device
patent, March 2004
- Jones, Christopher W.; Wilton, Steven J. E.
- US Patent Document 6,710,623
Reconfigurable Processing Array Having Hierarchical Communication Network
patent-application, May 2007
- Jones, Anthony Mark; Wasson, Paul M.; Butts, Michael R.
- US Patent Application 11/557478; 11/557478
Petaflops Router
patent-application, October 2011
- Baker, Zachary Kent; Power, John Fredrick; Tripp, Justin Leonard
- US Patent Application 12/763840; 20110258361