Title: Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution

Abstract

In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second level cache. After the write though, the corresponding line is deleted from the first level cache and/or prefetch unit, so that any further accesses to the same location in main memory have to be retrieved from the second level cache. The second level cache keeps track of multiple versions of data, where more than one speculative thread is running in parallel, while the first level cache does not have any of the versions during speculation. A switch allows choosing between modes of operation of a speculation blind first level cache.

Inventors:

Gara, Alan; Ohmacht, Martin

Issue Date:

2014-09-16

Research Org.:

International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1158923

Patent Number(s):

8838906

Application Number:

12/984,308

Assignee:

International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F12/0804 - with main memory updating
G06F12/0811 - with multilevel cache hierarchies
G06F12/0862 - with prefetch
G06F12/0897 - with two or more cache hierarchy levels
G06F2212/452 - Instruction code
G06F2212/507 - using speculative control
G06F2212/602 - Details relating to cache prefetching
G06F9/3004 - {to perform operations on memory}
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F9/3834 - {Maintaining memory consistency
G06F9/3842 - {Speculative instruction execution}
G06F9/3851 - {from multiple instruction streams, e.g. multistreaming
G06F9/3861 - {Recovery, e.g. branch miss-prediction, exception handling

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Y02D10/00 - Energy efficient computing

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DOE Contract Number:  

B554331

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING