Title: Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

Abstract

A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Inventors:

Gala, Alan; Ohmacht, Martin

Issue Date:

2014-09-02

Research Org.:

International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1156946

Patent Number(s):

8832415

Application Number:

12/984,329

Assignee:

International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F12/0804 - with main memory updating
G06F12/0811 - with multilevel cache hierarchies
G06F12/0862 - with prefetch
G06F12/0897 - with two or more cache hierarchy levels
G06F2212/452 - Instruction code
G06F2212/507 - using speculative control
G06F2212/602 - Details relating to cache prefetching
G06F9/3004 - {to perform operations on memory}
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F9/3834 - {Maintaining memory consistency
G06F9/3842 - {Speculative instruction execution}
G06F9/3851 - {from multiple instruction streams, e.g. multistreaming
G06F9/3861 - {Recovery, e.g. branch miss-prediction, exception handling

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Y02D10/00 - Energy efficient computing

Show less

DOE Contract Number:  

B554331

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING