Resistive foil edge grading for accelerator and other high voltage structures
Abstract
In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1133939
- Patent Number(s):
- 8749949
- Application Number:
- 13/285,996
- Assignee:
- Lawrence Livermore National Security, LLC (Livermore, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR H05H - PLASMA TECHNIQUE
- DOE Contract Number:
- AC52-07NA27344
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Caporaso, George J., Sampayan, Stephen F., and Sanders, David M. Resistive foil edge grading for accelerator and other high voltage structures. United States: N. p., 2014.
Web.
Caporaso, George J., Sampayan, Stephen F., & Sanders, David M. Resistive foil edge grading for accelerator and other high voltage structures. United States.
Caporaso, George J., Sampayan, Stephen F., and Sanders, David M. Tue .
"Resistive foil edge grading for accelerator and other high voltage structures". United States. https://www.osti.gov/servlets/purl/1133939.
@article{osti_1133939,
title = {Resistive foil edge grading for accelerator and other high voltage structures},
author = {Caporaso, George J. and Sampayan, Stephen F. and Sanders, David M.},
abstractNote = {In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jun 10 00:00:00 EDT 2014},
month = {Tue Jun 10 00:00:00 EDT 2014}
}
Works referenced in this record:
Energy dissipation resistor for implantable defibrillation circuitry
patent, May 1994
- O'Phelan, Michael J.
- US Patent Document 5,312,442
Fixed parallel plate MEMS capacitor microsensor array
patent, February 2009
- Patel, Sanjay V.; Fruhberger, Bernd; Klaassen, Erno H.
- US Patent Document 7,489,017
Compact accelerator for medical therapy
patent, May 2010
- Caporaso, George J.; Chen, Yu-Jiuan; Hawkins, Steven A.
- US Patent Document 7,710,051
ESD protected integrated capacitor with large capacity
patent, November 2010
- Klee, Mareike; Kiewitt, Rainer; Schiebel, Ulrich
- US Patent Document 7,838,965
Capacitor array and method for manufacturing the same
patent, August 2011
- Nagamiya, Katsumori; Ishida, Atsushi; Motoki, Akihiro
- US Patent Document 8,004,819
Multilayer capacitor array having terminal conductor, to which internal electrodes are connected in parallel, connected in series to external electrodes
patent, January 2012
- Aoki, Takashi
- US Patent Document 8,107,214
Works referencing / citing this record:
Diamagnetic composite material structure for reducing undesired electromagnetic interference and eddy currents in dielectric wall accelerators and other devices
patent, June 2015
- Caporaso, George J.; Poole, Brian R.; Hawkins, Steven A.
- US Patent Document 9,072,156
