# Reduced circuit implementation of encoder and syndrome generator

## Abstract

An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(2.sup.8) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

- Inventors:

- Issue Date:

- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)

- Sponsoring Org.:
- USDOE

- OSTI Identifier:
- 1132563

- Patent Number(s):
- 8,739,006

- Application Number:
- 13/168,559

- Assignee:
- International Business Machines Corporation (Armonk, NY)

- DOE Contract Number:
- B554331

- Resource Type:
- Patent

- Resource Relation:
- Patent File Date: 2011 Jun 24

- Country of Publication:
- United States

- Language:
- English

- Subject:
- 97 MATHEMATICS AND COMPUTING

### Citation Formats

```
Trager, Barry M, and Winograd, Shmuel.
```*Reduced circuit implementation of encoder and syndrome generator*. United States: N. p., 2014.
Web.

```
Trager, Barry M, & Winograd, Shmuel.
```*Reduced circuit implementation of encoder and syndrome generator*. United States.

```
Trager, Barry M, and Winograd, Shmuel. Tue .
"Reduced circuit implementation of encoder and syndrome generator". United States. https://www.osti.gov/servlets/purl/1132563.
```

```
@article{osti_1132563,
```

title = {Reduced circuit implementation of encoder and syndrome generator},

author = {Trager, Barry M and Winograd, Shmuel},

abstractNote = {An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(2.sup.8) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.},

doi = {},

journal = {},

number = ,

volume = ,

place = {United States},

year = {2014},

month = {5}

}

Works referenced in this record:

##
Error correction circuit and method, and semiconductor memory device including the circuit

patent-application, March 2012

- Yim, Yong-Tae; Choi, Yun-Ho
- US Patent Application 13/239534; 20120072810

##
A combined Reed-Solomon encoder and syndrome generator with small hardware complexity

conference, January 1992

- Fettweis, G.; Hassner, M.
- [Proceedings] 1992 IEEE International Symposium on Circuits and Systems