Structured wafer for device processing
Abstract
A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1132054
- Patent Number(s):
- 8729673
- Application Number:
- 13/239,181
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2011 Sep 21
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING
Citation Formats
Okandan, Murat, and Nielson, Gregory N. Structured wafer for device processing. United States: N. p., 2014.
Web.
Okandan, Murat, & Nielson, Gregory N. Structured wafer for device processing. United States.
Okandan, Murat, and Nielson, Gregory N. Tue .
"Structured wafer for device processing". United States. https://www.osti.gov/servlets/purl/1132054.
@article{osti_1132054,
title = {Structured wafer for device processing},
author = {Okandan, Murat and Nielson, Gregory N},
abstractNote = {A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {5}
}
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Works referenced in this record:
Die singulation using deep silicon etching
patent, August 2004
- Ruby, Richard C.; Geefay, Frank S.; Han, Cheol Hyun
- US Patent Document 6,777,267
Die singulation method and package formed thereby
patent, August 2012
- Anderson, Robert C.; Shul, Randy J.; Clews, Peggy J.
- US Patent Document 8,236,611
Method for chip singulation
patent-application, March 2006
- Beyne, Eric; Swinnen, Bart; Vanhaelemeersch, Serge
- US Patent Application 11/234835; 20060068567
Method for Transferring an Epitaxial Layer from a Donor Wafer to a System Wafer Appertaining to Microsystems Technology
patent-application, December 2010
- Knechtel, Roy
- US Patent Application 12/669933; 20100330506
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- Iwata, Yasumasa; Inao, Yoshihiro; Nakamura, Akihiko
- US Patent Document 9,627,235
Fast process flow, on-wafer interconnection and singulation for MEPV
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- Okandan, Murat; Nielson, Gregory N.; Cruz-Campa, Jose Luis
- US Patent Document 9,559,219