Structured wafer for device processing

Title: Structured wafer for device processing

Abstract

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Inventors:: Okandan, Murat; Nielson, Gregory N

Issue Date:: 2014-05-20

Research Org.:: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1132054

Patent Number(s):: 8,729,673

Application Number:: 13/239,181

Assignee:: Sandia Corporation (Albuquerque, NM)

DOE Contract Number:: AC04-94AL85000

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 Sep 21

Country of Publication:: United States

Language:: English

Subject:: 42 ENGINEERING

Citation Formats


                    Okandan, Murat, and Nielson, Gregory N. Structured wafer for device processing.  United States: N. p., 2014. 
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                    Okandan, Murat, & Nielson, Gregory N. Structured wafer for device processing.  United States.

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                    Okandan, Murat, and Nielson, Gregory N. Tue .  
        "Structured wafer for device processing".  United States.  https://www.osti.gov/servlets/purl/1132054.

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@article{osti_1132054,

  title        = {Structured wafer for device processing},

  author       = {Okandan, Murat and Nielson, Gregory N},

  abstractNote = {A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2014},

  month        = {5}

}

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Works referenced in this record:

Die singulation method and package formed thereby
patent, August 2012

Anderson, Robert; Shul, Randy; Clews, Peggy
US Patent Document 8,236,611
URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN%2F8236611

Method for chip singulation
patent-application, March 2006

Beyne, Eric; Swinnen, Bart; Vanhaelemeersch, Serge
US Patent Application 11/234835; 20060068567
URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220060068567%22.PGNR.&OS=DN/20060068567&RS=DN/20060068567

Method for Transferring an Epitaxial Layer from a Donor Wafer to a System Wafer Appertaining to Microsystems Technology
patent-application, December 2010

Knechtel, Roy
US Patent Application 12/669933; 20100330506
URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220100330506%22.PGNR.&OS=DN/20100330506&RS=DN/20100330506

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Title: Structured wafer for device processing

Abstract

Citation Formats

Die singulation method and package formed thereby patent, August 2012

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Method for Transferring an Epitaxial Layer from a Donor Wafer to a System Wafer Appertaining to Microsystems Technology patent-application, December 2010

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patent, August 2012

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patent-application, March 2006

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