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Title: Associative list processing unit

Abstract

An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full.

Inventors:
;
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1128691
Patent Number(s):
8688903
Application Number:
13/714,098
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Classifications (CPCs):
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
DOE Contract Number:  
AC04-94AL8500
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012 Dec 13
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS

Citation Formats

Hemmert, Karl Scott, and Underwood, Keith D. Associative list processing unit. United States: N. p., 2014. Web.
Hemmert, Karl Scott, & Underwood, Keith D. Associative list processing unit. United States.
Hemmert, Karl Scott, and Underwood, Keith D. Tue . "Associative list processing unit". United States. https://www.osti.gov/servlets/purl/1128691.
@article{osti_1128691,
title = {Associative list processing unit},
author = {Hemmert, Karl Scott and Underwood, Keith D},
abstractNote = {An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {4}
}

Works referenced in this record:

Content addressable memory with programmable word width and programmable priority
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Content addressable memory with hashing function
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Multipurpose CAM circuit
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Method and apparatus for terminating selected traffic flows
patent, October 2007


Block programmable priority encoder in a CAM
patent, February 2008


High performance and scalable width expansion architecture for fully parallel CAMs
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Preallocated disk queuing
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A Hardware Acceleration Unit for MPI Queue Processing
conference, January 2005