Performing a local barrier operation

Archer, Charles J; Blocksome, Michael A; Ratterman, Joseph D; Smith, Brian E

Title: Performing a local barrier operation

Abstract

Performing a local barrier operation with parallel tasks executing on a compute node including, for each task: retrieving a present value of a counter; calculating, in dependence upon the present value of the counter and a total number of tasks performing the local barrier operation, a base value of the counter, the base value representing the counter's value prior to any task joining the local barrier; calculating, in dependence upon the base value and the total number of tasks performing the local barrier operation, a target value, the target value representing the counter's value when all tasks have joined the local barrier; joining the local barrier, including atomically incrementing the value of the counter; and repetitively, until the present value of the counter is no less than the target value of the counter: retrieving the present value of the counter and determining whether the present value equals the target value.

Inventors:: Archer, Charles J; Blocksome, Michael A; Ratterman, Joseph D; Smith, Brian E

Issue Date:: Tue Mar 04 00:00:00 EST 2014

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1126878

Patent Number(s):: 8667501

Application Number:: 13/206,590

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F9/522 - {Barrier synchronisation}
G06F9/54 - Interprogram communication

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DOE Contract Number:: B554331

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Archer, Charles J, Blocksome, Michael A, Ratterman, Joseph D, and Smith, Brian E. Performing a local barrier operation.  United States: N. p., 2014. 
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                    Archer, Charles J, Blocksome, Michael A, Ratterman, Joseph D, & Smith, Brian E. Performing a local barrier operation.  United States.

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                    Archer, Charles J, Blocksome, Michael A, Ratterman, Joseph D, and Smith, Brian E. Tue .  
        "Performing a local barrier operation".  United States.  https://www.osti.gov/servlets/purl/1126878.

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@article{osti_1126878,

  title        = {Performing a local barrier operation},

  author       = {Archer, Charles J and Blocksome, Michael A and Ratterman, Joseph D and Smith, Brian E},

  abstractNote = {Performing a local barrier operation with parallel tasks executing on a compute node including, for each task: retrieving a present value of a counter; calculating, in dependence upon the present value of the counter and a total number of tasks performing the local barrier operation, a base value of the counter, the base value representing the counter's value prior to any task joining the local barrier; calculating, in dependence upon the base value and the total number of tasks performing the local barrier operation, a target value, the target value representing the counter's value when all tasks have joined the local barrier; joining the local barrier, including atomically incrementing the value of the counter; and repetitively, until the present value of the counter is no less than the target value of the counter: retrieving the present value of the counter and determining whether the present value equals the target value.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Mar 04 00:00:00 EST 2014},

  month        = {Tue Mar 04 00:00:00 EST 2014}

}

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Title: Performing a local barrier operation

Abstract

Citation Formats

Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network patent, April 1992

Self-timed mesh routing chip with data broadcasting patent, July 1994

Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations patent, April 1996

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Protocol for self-organizing network using a logical spanning tree backbone patent, January 2006

Hyperbolic tree space display of computer system monitoring and analysis data patent, November 2006

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Hierarchical tree-based protection scheme for mesh networks patent, April 2007

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System for allocating computing resources of distributed computer system with transaction manager patent, September 2009

Method and apparatus for storing tree data structures among and within multiple memory channels patent, November 2009

Implementing locks in a distributed processing system patent, December 2009

Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks patent, March 2010

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Hierarchical tree-based protection scheme for mesh networks patent, August 2010

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Performing an allreduce operation using shared memory patent, April 2012

System and method for configuring computer applications and devices using inheritance patent-application, July 2002

Synchronization objects for multi-computer systems patent-application, February 2003

Distributed processing multi-processor computer patent-application, September 2003

Efficient circuits for out-of-order microprocessors patent-application, February 2004

Arithmetic functions in torus and tree networks patent-application, April 2004

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Apparatus and method for capacity planning for data center server consolidation and workload reassignment patent-application, March 2008

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Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network
patent, April 1992

Self-timed mesh routing chip with data broadcasting
patent, July 1994

Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations
patent, April 1996

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patent, July 1996

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patent, December 1996

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patent, September 1997

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patent, November 1998

Intelligent batching of distributed messages
patent, February 1999

Partitioning of processing elements in a SIMD/MIMD array processor
patent, March 1999

Parallel computer system using properties of messages to route them through an interconnect network and to select virtual channel circuits therewithin
patent, April 1999

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patent, August 1999

Prediction system for RF power distribution
patent, September 1999

Parallel computing system
patent, December 1999

SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum
patent, March 2000

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patent, May 2000

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patent, June 2000

Method and apparatus for internetworking buffer management
patent, August 2000

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patent, August 2001

Method, system and computer program product for managing memory in a non-uniform memory access system
patent, September 2001

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patent, October 2002

Dynamically matching users for group communications based on a threshold degree of matching of sender and recipient predetermined acceptance criteria
patent, November 2002

Database system providing optimization of group by operator over a union all
patent, February 2004

System and method for configuration, management, and monitoring of a computer network using inheritance
patent, December 2004

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patent, January 2006

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patent, November 2006

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patent, January 2007

Hierarchical tree-based protection scheme for mesh networks
patent, April 2007

Phased upgrade of a computing environment
patent, August 2007

Systems for communicating current and future activity information among mobile internet users and methods therefor
patent, October 2007

Method and apparatus for storing tree data structures among and within multiple memory channels
patent, April 2008

Method and apparatus for suspending execution of a thread until a specified memory access occurs
patent, April 2008

Massively parallel supercomputer
patent, June 2009

Synchronizing access to global resources
patent, August 2009

System for allocating computing resources of distributed computer system with transaction manager
patent, September 2009

Method and apparatus for storing tree data structures among and within multiple memory channels
patent, November 2009

Implementing locks in a distributed processing system
patent, December 2009

Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks
patent, March 2010

Locating hardware faults in a parallel computer
patent, April 2010

Memory control device
patent, April 2010

System and method for automatic generation of a hierarchical tree network and the use of two complementary learning algorithms, optimized for each leaf of the hierarchical tree network
patent, May 2010

Method and apparatus for stacked address, bus to memory data transfer
patent, June 2010

Hierarchical tree-based protection scheme for mesh networks
patent, August 2010

Computer hardware fault administration
patent, September 2010

Dynamic multipoint tree rearrangement
patent, October 2010

Root node redundancy for multipoint-to-multipoint transport trees
patent, November 2010

Cross-layer design techniques for interference-aware routing configuration in wireless mesh networks
patent, May 2011

Signaling completion of a message transfer from an origin compute node to a target compute node
patent, May 2011

Efficient content authentication in peer-to-peer networks
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Performing an allreduce operation on a plurality of compute nodes of a parallel computer
patent, April 2012

Performing an allreduce operation using shared memory
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System and method for configuring computer applications and devices using inheritance
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Synchronization objects for multi-computer systems
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Distributed processing multi-processor computer
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Efficient circuits for out-of-order microprocessors
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Arithmetic functions in torus and tree networks
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Method and apparatus for managing an event processing system
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Fast and memory protected asynchronous message scheme in a multi-process and multi-thread environment
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Apparatus and method for capacity planning for data center server consolidation and workload reassignment
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Remote DMA systems and methods for supporting synchronization of distributed processes in a multi-processor system using collective operations
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Correlating Hardware Devices Between Local Operating System and Global Management Entity
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Integrated Development Environment with Object-Oriented GUI Rendering Feature
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Interprocess Resource-Based Dynamic Scheduling System and Method
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Performing an Allreduce Operation Using Shared Memory
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Non-Volatile Memory And Method With Non-Sequential Update Block Management
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Fault Tolerant Self-Optimizing Multi-Processor System and Method Thereof
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Database Retrieval with a Non-Unique Key on a Parallel Computer System
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Determining When a Set of Compute Nodes Participating in a Barrier Operation on a Parallel Computer are Ready to Exit the Barrier Operation
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patent-application, September 2009

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patent-application, October 2009

Novel Massively Parallel Supercomputer
patent-application, October 2009

Performing An Allreduce Operation On A Plurality Of Compute Nodes Of A Parallel Computer
patent-application, November 2009

Method and System for Increasing Throughput in a Hierarchical Wireless Network
patent-application, December 2009

Message Flow Control in a Multi-Node Computer System
patent-application, December 2009

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patent-application, January 2010