Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)
Abstract
A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Marchines Corporation, Armonk, NY, USA
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1117859
- Patent Number(s):
- 8640070
- Application Number:
- 12/941,834
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2010 Nov 08
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Asaad, Sameh W, Bellofatto, Ralph E, Brezzo, Bernard, Haymes, Charles L, Kapur, Mohit, Parker, Benjamin D, Roewer, Thomas, and Tierno, Jose A. Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs). United States: N. p., 2014.
Web.
Asaad, Sameh W, Bellofatto, Ralph E, Brezzo, Bernard, Haymes, Charles L, Kapur, Mohit, Parker, Benjamin D, Roewer, Thomas, & Tierno, Jose A. Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs). United States.
Asaad, Sameh W, Bellofatto, Ralph E, Brezzo, Bernard, Haymes, Charles L, Kapur, Mohit, Parker, Benjamin D, Roewer, Thomas, and Tierno, Jose A. Tue .
"Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)". United States. https://www.osti.gov/servlets/purl/1117859.
@article{osti_1117859,
title = {Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)},
author = {Asaad, Sameh W and Bellofatto, Ralph E and Brezzo, Bernard and Haymes, Charles L and Kapur, Mohit and Parker, Benjamin D and Roewer, Thomas and Tierno, Jose A},
abstractNote = {A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {1}
}
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Works referencing / citing this record:
System on a chip FPGA spatial debugging using single snapshot
patent, December 2016
- Shanker, Pankaj Mohan; Kiu, Ming-Hoe; Chukhlebov, Mikhail Ivanovich
- US Patent Document 9,513,334